Hi Wan,
The Shared BRAM uses a dual-port BRAM with one port connected to
your design, and the other connected to an OPB bus instantiated in
the fabric.
On a V2P (IBOB, BEE2) the OPB bus is branched off the PLB bus,
which is connected to the PPC405 on the FPGA. On a V5 (ROACH),
the OPB is connected to a OPB/EPB bridge that goes the the
EPB controller on the external PPC440.
What this boils down to is that the BRAM is connected to the
processor's bus as a peripheral, with a given address. For the
CPU to access its contents is basically a bus memory access.
--Henry
[email protected] wrote:
Hi Andrew:
Thanks for your information. But it could not help me. I mean the
documents do not tell me how the CPU read the data from the block ram. I
only know how to write data into block ram through the documents.
Wan
------------------------------------------------------------------------
*From:* Andrew Siemion [mailto:[email protected]]
*Sent:* Tuesday, 20 January 2009 8:39 AM
*To:* Cheng, Wan (ATNF, Marsfield); [email protected]
*Subject:* Re: [casper] usage of snapshot 64
Hi Wan,
Most CASPER blocks are documented at
http://casper.berkeley.edu/documentation.php (see documentation links at
top of right frame)
The documentation for the snap64 block for v 7.1 of the tools is at
http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node59.html
Regards,
Andrew
On 1/18/09 3:36 PM, "[email protected]" <[email protected]> wrote:
Hi
Anybody could tell me how to use snap64? From the description, I
could not see how the CPU could access the memory in FPGA. It seems
that the CPU could not write address into the snap64 to specify the
accessing address.
Wan
