> Hi Wan, > > The Shared BRAM uses a dual-port BRAM with one port connected to > your design, and the other connected to an OPB bus instantiated in > the fabric. > > On a V2P (IBOB, BEE2) the OPB bus is branched off the PLB bus, > which is connected to the PPC405 on the FPGA. On a V5 (ROACH), > the OPB is connected to a OPB/EPB bridge that goes the the > EPB controller on the external PPC440. > > What this boils down to is that the BRAM is connected to the > processor's bus as a peripheral, with a given address. For the > CPU to access its contents is basically a bus memory access.
To add a little, I'm sure you know that if you go to the tinyshell, and do a read or write on the bram's symbol, you can manipulate the contents. In the same way, you can write some C code and include it in the software build that accesses the BRAM. Once you write your code, and put it in the right directory in the project, the system will automatically build it, and you can have it become part of the tinyshell, or you can have it automatically run at start-up. Look at \your_proj\XPS_iBOB_base\drivers\xps_bram\bram.c and bram.h, along with the tinysh code to see how to do it. In fact, you may want to look around at all these directories and figure out what's going on in there. A word of warning is that these directories are automatically created when you run bee_xps with the "create base system" checked, so make sure your stuff is saved somewhere else if you modify the existing files. John > > --Henry > > > [email protected] wrote: >> Hi Andrew: >> >> Thanks for your information. But it could not help me. I mean the >> documents do not tell me how the CPU read the data from the block ram. I >> only know how to write data into block ram through the documents. >> >> Wan >> >> ------------------------------------------------------------------------ >> *From:* Andrew Siemion [mailto:[email protected]] >> *Sent:* Tuesday, 20 January 2009 8:39 AM >> *To:* Cheng, Wan (ATNF, Marsfield); [email protected] >> *Subject:* Re: [casper] usage of snapshot 64 >> >> Hi Wan, >> >> Most CASPER blocks are documented at >> http://casper.berkeley.edu/documentation.php (see documentation links at >> top of right frame) >> >> The documentation for the snap64 block for v 7.1 of the tools is at >> http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node59.html >> >> Regards, >> >> Andrew >> >> >> >> >> On 1/18/09 3:36 PM, "[email protected]" <[email protected]> wrote: >> >> Hi >> >> Anybody could tell me how to use snap64? From the description, I >> could not see how the CPU could access the memory in FPGA. It seems >> that the CPU could not write address into the snap64 to specify the >> accessing address. >> >> Wan >> >
