Hello, I heard at the last CASPER workshop that no non-free IP cores were needed from Xilinx. For example, the 10 GbE core is not needed. Is this true? What about for building designs for the control FPGA on the BEE2? Thanks, Glenn
- [casper] Xilinx IP G Jones
- Re: [casper] Xilinx IP John Ford
- Re: [casper] Xilinx IP Jason Manley