Henry and/or Dave can correct me if I'm wrong, but my understanding
was that if you checked the "use lightweight MAC" box in the 10GbE
core, then it would instantiate the Berkeley core rather than the
Xilinx one. In this case you shouldn't need the Xilinx 10GbE core.
The underlying Berkeley core has a few limitations (like you can only
clock-in 64 bit numbers because it can't handle non-64bit boundaries).
These are transparent to you and for the most part you don't need to
worry about 'em. The only limitation of interest is that the Berkeley
receive side does not do full error-correction on the Virtex-II
devices to save resources. This will not be the case on ROACH as it
has a fixed-IP core for doing this.
Jason
On 20 Jan 2009, at 21:58, John Ford wrote:
Hello,
I heard at the last CASPER workshop that no non-free IP cores were
needed
from Xilinx. For example, the 10 GbE core is not needed. Is this
true?
It turns out that the 10 GbE core *is* needed, at least for version
7.1.
The rest of the IP modules that are needed have been freed by Xilinx.
They used to be non-free.
What
about for building designs for the control FPGA on the BEE2?
Dunno what's needed for this, but the Fast Ethernet core for both
OPB and
PLB are free, along with the uart modules.
John
Thanks,
Glenn
