> Hello, > I heard at the last CASPER workshop that no non-free IP cores were needed > from Xilinx. For example, the 10 GbE core is not needed. Is this true?
It turns out that the 10 GbE core *is* needed, at least for version 7.1. The rest of the IP modules that are needed have been freed by Xilinx. They used to be non-free. > What > about for building designs for the control FPGA on the BEE2? Dunno what's needed for this, but the Fast Ethernet core for both OPB and PLB are free, along with the uart modules. John > Thanks, > Glenn >
