Hi, This is the first time I'm posting to this mailing list, so allow me to introduce myself. My name is Jason Zheng, and I am an FPGA design engineer at JPL. A couple of weeks ago I attended the CASPER workshop at JPL, and have started to play with the CASPER libraries. My main interest is to infuse CASPER cores into the instrument design at JPL.
I've been playing with the 10GE UDP core for a while, and took a look at the VHDL source code. Comparing the simulink model with the VHDL source code, I noticed that the simulink model hid the physical interface (XAUI_XXX) from CASPER users. The simulink model only shows the internal datapath ports and the LED outputs. It doesn't seem obvious to me how to run a simulink simulation with the UDP core fully modeling a computer network. Am I missing some key information? Or is the UDP core meant to be a black hole/hose only? cheers, Jason Zheng
