Hi, We're also at JPL working on bringing the first ROACH board we have received to life. We have already been able to capture some sample data out of an iADC board connected to a ROACH and would now like to gain some familiarity with the 10GE ports on the board.
In the BEE_XPS system library, there are two 10GE blocks, the ten_GbE and the ten_Gbe_v2. For Roach board designs, which block is preferred. I am guessing the ten_Gbe_v2 block is preferred, but I wanted to confirm it. Also, I am wondering what documentation is available for that block. So far, I have found the Wiki page, http://casper.berkeley.edu/wiki/Ten_GbE_v2, but I was wondering if there is any additional documentation. The Wiki page mentions some OPB registers: MAC, IP, UDP and ARP. I generated a test design using the ten_Gbe_v2 (but have not tried running it yet) and the "core_info.tab" file generated in the XPS_ROACH_BASE folder did not have any reference to these registers. Will they appear when I load the BOF file? Also, it mentions in the Wiki documentation, that some configuration packets may be sent and received by the microprocessor core. Where would I look to see how that works? Thanks, Robert Navarro From: [email protected] [mailto:[email protected]] On Behalf Of Jason Zheng Sent: Wednesday, July 01, 2009 3:04 PM To: [email protected] Subject: [casper] 10GE UDP core Hi, This is the first time I'm posting to this mailing list, so allow me to introduce myself. My name is Jason Zheng, and I am an FPGA design engineer at JPL. A couple of weeks ago I attended the CASPER workshop at JPL, and have started to play with the CASPER libraries. My main interest is to infuse CASPER cores into the instrument design at JPL. I've been playing with the 10GE UDP core for a while, and took a look at the VHDL source code. Comparing the simulink model with the VHDL source code, I noticed that the simulink model hid the physical interface (XAUI_XXX) from CASPER users. The simulink model only shows the internal datapath ports and the LED outputs. It doesn't seem obvious to me how to run a simulink simulation with the UDP core fully modeling a computer network. Am I missing some key information? Or is the UDP core meant to be a black hole/hose only? cheers, Jason Zheng
