Hi Jason, Thanks for that explanation. Short of simulating a full-fledged computer network, is there a way to "send" a UDP packet to the simulation model as a stimulus? I'd imagine a back-end matlab function, once called, toggles the rx_valid port. Something like that?
~Jason On Wed, Jul 1, 2009 at 3:11 PM, Jason Manley <[email protected]> wrote: > Hi Jason > > Yes, you have the right of it. The Simulink yellow block 10GbE core is a > black hole into an ethernet cloud. We don't try to model an entire > multi-board system, but rather just the design at single board level. > > Modelling networks is a complicated affair and entire software suites have > been written to try'n address the issue. We have not broached it yet :) > > Jason > > > On 01 Jul 2009, at 15:03, Jason Zheng wrote: > > Hi, >> >> This is the first time I'm posting to this mailing list, so allow me to >> introduce myself. My name is Jason Zheng, and I am an FPGA design engineer >> at JPL. A couple of weeks ago I attended the CASPER workshop at JPL, and >> have started to play with the CASPER libraries. My main interest is to >> infuse CASPER cores into the instrument design at JPL. >> >> I've been playing with the 10GE UDP core for a while, and took a look at >> the VHDL source code. Comparing the simulink model with the VHDL source >> code, I noticed that the simulink model hid the physical interface >> (XAUI_XXX) from CASPER users. The simulink model only shows the internal >> datapath ports and the LED outputs. It doesn't seem obvious to me how to run >> a simulink simulation with the UDP core fully modeling a computer network. >> Am I missing some key information? Or is the UDP core meant to be a black >> hole/hose only? >> >> cheers, >> >> Jason Zheng >> > >
