Hi Daniel,

How fast are you trying to clock you design?  Try opening the timing report
by typing dos('timingan') from the Matlab prompt and File-->Open
./XPS_ROACH_base/implementation/system.twx from inside the design directory.
 This should tell you where the offending paths are (i.e. negative slack).
 You could then add latency strategically to give the data some time to
propagate.

Mark


On Wed, Nov 24, 2010 at 1:51 PM, Daniel Esteban Herrera Pena <
[email protected]> wrote:

> Hi CASPER team,
>
> I wanted to test the iADC tutorial on my ROACH but I can't.
>
> I followed the tutorial changing XSG core from iBOB to sx95t and removing
> ibop_lwip from original design. Simulation worked perfect but when I start
> bee_xps the following error appears after a while twice:
>
> ERROR: 2 constraints not met.
>
> PAR could not meet all timing constraints. A bitstream will not be
> generated.
>
> I saw what Mark Wagner recommended to see:
> <model_directory>/XPS_ROACH_base/implementation/system_map.mrp
>
> The thing I have here is a large file but I suspect that the problem is
> around this part:
>
> Asterisk (*) preceding a constraint indicates it was not met.
>   This may be due to a setup or hold violation.
>
>
> ----------------------------------------------------------------------------------------------------------
>  Constraint                                |    Check    | Worst Case |
> Best Case | Timing |   Timing
>                                            |             |    Slack   |
> Achievable | Errors |    Score
>
> ----------------------------------------------------------------------------------------------------------
> * NET "iadc_test_adc/iadc_test_adc/adc_clk_ | MAXPERIOD   |    -1.666ns|
>         |       1|        1666
>  buf" PERIOD = 10 ns HIGH 50%              | MINLOWPULSE |     4.666ns|
>  5.334ns|       0|           0
>
> ----------------------------------------------------------------------------------------------------------
> * PERIOD analysis for net "iadc_test_adc/ia | SETUP       |     8.535ns|
>  1.465ns|       0|           0
>  dc_test_adc/adc_clk_dcm" derived from  NE | HOLD        |     0.148ns|
>         |       0|           0
>  T "iadc_test_adc/iadc_test_adc/adc_clk_bu | MINPERIOD   |     7.779ns|
>  2.221ns|       0|           0
>  f" PERIOD = 10 ns HIGH 50%  duty cycle co | MAXPERIOD   |    -1.666ns|
>         |       1|        1666
>  rrected to 10 nS  HIGH 5 nS               |             |            |
>         |        |
>
> ----------------------------------------------------------------------------------------------------------
>
> Both constraints have a MAXPERIOD of -1.666ns, I don't know that a minus
> have to do here with time, but is what the report says.
>
> Do you have any insights of this?. Or I just disable the PAR timing check?
>
> Best!
>
> Daniel Herrera
>
>
>

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