Hi David,
Thank you very much! I could synthesize running at 400MHz, I had to
change DFS_FREQUENCY_MODE and DLL_FREQUENCY_MODE twice in the vhd file.
The problem now arises with my equipment, I realize that I have only
120MHz function generator and the I need at least 128MHz (128MHZ/4 =
32MHz minimun to DCM). Is there a way to use the internal clock in ROACH
as the iADC external clock (clk_i)?
Regards,
Daniel.
On Mon, 13 Dec 2010 21:50:44 +0200, David George
<[email protected]> wrote:
Hi Daniel
I tried to clock at 100MHz system clock and 400Mz for ADC, now I
changed
to 200/800 respectively and it compiled! Why adc_clk_buf has issues
with
lower frequency? Where I can find it in my design?
It looks like your timing error was inside the iADC yellow block,
which corresponds to a pcore in your EDK project. I suspect you have
run into a minimum timing constraint on a DCM which is configured for
high speed clocks. The minimum input clock frequency for DCMs on
Virtex-5 is 120 MHz. So this timing error isn't one that adding
latency can fix.
If you want to run at less than 120 MHz, you need change two
parameters (vhdl generics) in
xps_lib/XPS_ROACH_base/pcores/adc_interface_v1_01_a/hdl/vhdl/adc_interface.vhd.
Both DFS_FREQUENCY_MODE and DLL_FREQUENCY_MODE should be equal to
"LOW" (as opposed to "HIGH")
This represents a bug in the toolflow (or I suppose a missing
feature)
as this could very comfortably be done automatically. I'll file a bug
report on this and it will probably be fixed soon.
Hopefully I'm correct in understanding the problem and have helped
ease your mind about it too.
Cheers,
David George
