> Thank you. I thought the model was > so simple that it should be okay. > Did you compile after downgrading > your glibc?
Yes, we had to downgrade glibc when it was first installed a month or so ago. > Does it also compile > with the updated glibc? No. The glibc thing is a bug in xst. xilinx will have to fix that. John > >>> A new problem is preventing me from >>> compiling even simple models with >>> bee_xps. For example, when I compile >>> a model containing only the system >>> generator, XSB Core Config, Xilinx >>> constants and CASPER software >>> registers, I receive the following >>> messages from bee_xps. >>> >>> Detected Linux OS >>> ############################# >>> ## System Update ## >>> ############################# >>> ############################# >>> ## Block objects creation ## >>> ############################# >>> ###################### >> >> Hi Ron and all. I just tried to run your example, and I got errors. I >> forgot that you can't have mixed case model file names. It gums up the >> works somewhere in there. >> >> I got the following result with testRegisters.mdl: >> >> Detected Linux OS >> ############################# >> ## System Update ## >> ############################# >> ############################# >> ## Block objects creation ## >> ############################# >> ###################### >> ## Checking objects ## >> ###################### >> Running system generator ... >> >> xsg_blk = >> >> testRegisters/ System Generator >> >> >> xsg_result = >> >> 0 >> >> XSG generation complete. >> ######################### >> ## Copying base system ## >> ######################### >> >> source_dir = >> >> /export/home/blink/scratch/casper/mlib_devel/xps_lib/XPS_ROACH_base >> >> Copying base package from: >> /export/home/blink/scratch/casper/mlib_devel/xps_lib/XPS_ROACH_base >> >> msg = >> >> '' >> >> >> >> msgid = >> >> '' >> >> >> ######################## >> ## Copying custom IPs ## >> ######################## >> ########################## >> ## Creating Simulink IP ## >> ########################## >> Error using ==> gen_xps_create_pcore at 41 >> Cannot find any compiled XSG netlist. Have you run the Xilinx System >> Generator on your design ? >>>> >> >> I renamed testRegisters.mdl to test_registers.mdl, and it compiles fine. >> >> John >> >> >> >> > >
