[casper] Bidirectional IO?

[Rich Lacasse]

Hi All,

I'm looking for a way to make FPGA GPIO A a bidirectional bus, 
controlled by a "R/W" line that would be input on FPGA GPIO B.  Looking 
at the schematic, I see that the connector pins are driven by 
bidirectional buffers with direction control coming from the Xilinx.  So 
at the hardware level, this ought to be possible.  However, I cannot 
find a way to control the directionality within the Simulink/CASPER 
development tools.  It seems like you can pick either input or output , 
but not bidirectional for GPIO[AB].  Has anyone else ever tried to make 
one of these 8-bit buses bidirectional?  Is there a way, given the 
constraints of the design tools?

thanks!
Rich