Hi Rich, The Xilinx inverter block in the Simulink library allows an enable input. Whether this is a tri-state enable or not I don't know. The next hurdle would be, will the PAR allow input and output logic to be connected to an IO pin at the same time?
Worth a try and I would be very interested to see if this is possible. Regards, Dave Callaghan Lecturer: Radio Engineering Department of Electronic Engineering Durban University of Technology Tel. 27 31 373 2561 Fax. 27 31 373 2744 Email [email protected] -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Rich Lacasse Sent: 16 April 2012 09:01 PM To: casper list Subject: [casper] Bidirectional IO? Hi All, I'm looking for a way to make FPGA GPIO A a bidirectional bus, controlled by a "R/W" line that would be input on FPGA GPIO B. Looking at the schematic, I see that the connector pins are driven by bidirectional buffers with direction control coming from the Xilinx. So at the hardware level, this ought to be possible. However, I cannot find a way to control the directionality within the Simulink/CASPER development tools. It seems like you can pick either input or output , but not bidirectional for GPIO[AB]. Has anyone else ever tried to make one of these 8-bit buses bidirectional? Is there a way, given the constraints of the design tools? thanks! Rich "This e-mail is subject to our Disclaimer, to view click http://www.dut.ac.za/pages/22414";
