Re: [casper] Bidirectional IO?

[Rich Lacasse]

Hi Henno, Sorry about that: ROACH Rich Henno Kriel wrote: Hi Rich What hardware platform are you using? Regards, Henno On Mon, Apr 16, 2012 at 9:00 PM, Rich Lacasse <rlaca...@nrao.edu> wrote: Hi All, I'm looking for a way to make FPGA GPIO A a bidirectional bus, controlled by a "R/W" line that would be input on FPGA GPIO B.  Looking at the schematic, I see that the connector pins are driven by bidirectional buffers with direction control coming from the Xilinx.  So at the hardware level, this ought to be possible.  However, I cannot find a way to control the directionality within the Simulink/CASPER development tools.  It seems like you can pick either input or output , but not bidirectional for GPIO[AB].  Has anyone else ever tried to make one of these 8-bit buses bidirectional?  Is there a way, given the constraints of the design tools? thanks! Rich -- Henno Kriel FPGA Engineer Digital Back End meerKAT SKA South Africa Third Floor The Park Park Road (off Alexandra Road) Pinelands 7405 Western Cape South Africa Latitude: -33.94329 (South); Longitude: 18.48945 (East). (p) +27 (0)21 506 7300 (p) +27 (0)21 506 7365 (direct) (f) +27 (0)21 506 7375 (m) +27 (0)84 504 5050