Hi CASPER team, I am working with the iBOB FPGA at 250 MHz and two iADCs at 1000 GHz in a correlator project. In the compilation I have a timing error
**************************************************************************** ERROR: 1 constraint not met. PAR could not meet all timing constraints. A bitstream will not be generated. To disable the PAR timing check: 1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS. OR 2> Type following at the XPS prompt: XPS% xset enable_par_timing_error 0 I have read lot of documents and everybody said that is better solve the problem adding delays and no disable the PAR timing check, but a like check this behavior. To do this I go to the Xilinx Platform Studio and open the file system.xmp. Then I go to Project > Project Options> Hierarchy and Flow> and unselected the “Treat timing closure failure as an error” and finally I save the project. Then execute again the bee_xps command in Matlab for the new compilation but I obtain the same error. Then go to check the state of the option of “Treat timing closure failure as an error” and it appear selected again. It’s like the bee_xps select automatically this option and I do not how unselected. Do you have any insights of this? Thanks a lot, Isaac
