Re: [casper] To disable the PAR timing check:

[Danny Price]

Hi Isaac An alternative route might be to compile at 200 MHz, and then open the design with PlanAhead. In Planahead you can then bump it up to 250 MHz, and try to compile from there, with much more fine-grain control. As a bonus, you'll also be able to see where it's failing timing. I believe you can turn off timing checks, allthough as everyone else has suggested, it's probably a bad idea. There's a bit of a write-up here: https://casper.berkeley.edu/wiki/Speed_Optimization_with_PlanAhead Xilinx have some tutorials too. Cheers Danny isaac...@caltech.edu 3 April 2013 23:45 Hi CASPER team, I am working with the iBOB FPGA at 250 MHz and two iADCs at 1000 GHz in a correlator project. In the compilation I have a timing error **************************************************************************** ERROR: 1 constraint not met. PAR could not meet all timing constraints. A bitstream will not be generated. To disable the PAR timing check: 1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS. OR 2> Type following at the XPS prompt: XPS% xset enable_par_timing_error 0 I have read lot of documents and everybody said that is better solve the problem adding delays and no disable the PAR timing check, but a like check this behavior. To do this I go to the Xilinx Platform Studio and open the file system.xmp. Then I go to Project > Project Options> Hierarchy and Flow> and unselected the “Treat timing closure failure as an error” and finally I save the project. Then execute again the bee_xps command in Matlab for the new compilation but I obtain the same error. Then go to check the state of the option of “Treat timing closure failure as an error” and it appear selected again. It’s like the bee_xps select automatically this option and I do not how unselected. Do you have any insights of this? Thanks a lot, Isaac