Hi, Isaac, On Apr 3, 2013, at 3:45 PM, [email protected] wrote:
> ERROR: 1 constraint not met. > > PAR could not meet all timing constraints. A bitstream will not be generated. > > I have read lot of documents and everybody said that is better solve the > problem adding delays and no disable the PAR timing check, but a like > check this behavior. Just to reiterate the warning you already know: running a design that fails timing is fraught with peril. How do you know if misbehavior is caused by errors in logic or simply failed timing? It can be especially troublesome when it appears to work in the cool lab with clean power (providing a false sense of confidence) but then fails in the field (maybe not right away) due to different operating conditions/environment. Proceed at your own risk!!! > To do this I go to the Xilinx Platform Studio and open the file > system.xmp. Then I go to Project > Project Options> Hierarchy and Flow> > and unselected the “Treat timing closure failure as an error” and finally > I save the project. > Then execute again the bee_xps command in Matlab for the new compilation > but I obtain the same error. Then go to check the state of the option of > “Treat timing closure failure as an error” and it appear selected again. > It’s like the bee_xps select automatically this option and I do not how > unselected. > Do you have any insights of this? The second time you run bee_xps, make sure just the "EDK/ISE/Bitgen" checkbox is checked, otherwise you will regenerate the system.xmp and other files. Dave
