That makes sense. Thanks alot! T
----- Original Message ----- From: "Henno Kriel" <[email protected]> To: "Timothy Madden" <[email protected]> Cc: "Casper Lists" <[email protected]> Sent: Thursday, April 25, 2013 11:39:05 PM Subject: Re: [casper] Changing Clock Source on MSSGE ROACH Block Hi Tim Are you using one of the CASPER DAC yellow blocks? You are also using dac1_clk and not dac0_clk - are you using 2 DAC boards? Henno On Thu, Apr 25, 2013 at 10:49 PM, Timothy Madden < [email protected] > wrote: Dear Caspar: I have a design that compiles fine when I have the clock on the MSSGE ROACH block set to sys_clk 100MHz. If I set the clock to dac1_clk, 100MHz, or other clocks I get lots of compile errors of the sort below. Basically, the Xilinx compiler thinks the clock pins are disconnected on many of the blocks. If I set the clock back to sys_clk, it compiles fine again. Here is an example error. I get many of these. Constructing platform-level connectivity ... ERROR:EDK:4072 - INSTANCE: sys_block_inst, PORT: fab_clk - port is driven by a sourceless connector - /home/oxygen26/TMADDEN/ROACH/projcts/singen/XPS_ROACH_base/system.mhs line 148 I am running in Linux, Matlab R2012b. XSG version is 14.2 Tim Madden Argonne Lab -- Henno Kriel DSP Engineer Digital Back End meerKAT SKA South Africa Third Floor The Park Park Road (off Alexandra Road) Pinelands 7405 Western Cape South Africa Latitude: -33.94329 (South); Longitude: 18.48945 (East). (p) +27 (0)21 506 7300 (p) +27 (0)21 506 7365 (direct) (f) +27 (0)21 506 7375 (m) +27 (0)84 504 5050
