That has to be the problem! Thanks.
T

----- Original Message -----
From: "Andrew Martens" <[email protected]>
To: "Henno Kriel" <[email protected]>
Cc: "Timothy Madden" <[email protected]>, "Casper Lists" 
<[email protected]>
Sent: Friday, April 26, 2013 12:35:48 AM
Subject: Re: [casper] Changing Clock Source on MSSGE ROACH Block

Hi Tim 





Are you using one of the CASPER DAC yellow blocks? 


You are also using dac1_clk and not dac0_clk - are you using 2 DAC boards? 


Henno 

To expand on what Henno has said, if you specify that you will be using a clock 
source besides those derived from the onboard oscillator (sys_clk, arb_clk), 
then you need to include the related yellow block i.e if you say you are going 
to use dac1_clk, then you must include a DAC yellow block with the appropriate 
parameters set. The toolflow does not check that you have added the required 
block and will find that it is missing the required clock signal at some later 
time in the compile. 

Cheers 
Andrew 






On Thu, Apr 25, 2013 at 10:49 PM, Timothy Madden < [email protected] > wrote: 


Dear Caspar: 

I have a design that compiles fine when I have the clock on the MSSGE ROACH 
block set to sys_clk 100MHz. If I set the clock to 
dac1_clk, 100MHz, or other clocks I get lots of compile errors of the sort 
below. Basically, the Xilinx 
compiler thinks the clock pins are disconnected on many of the blocks. 
If I set the clock back to sys_clk, it compiles fine again. 

Here is an example error. I get many of these. 

Constructing platform-level connectivity ... 
ERROR:EDK:4072 - INSTANCE: sys_block_inst, PORT: fab_clk - port is driven by a 
sourceless connector - 
/home/oxygen26/TMADDEN/ROACH/projcts/singen/XPS_ROACH_base/system.mhs line 
148 



I am running in Linux, Matlab R2012b. 
XSG version is 14.2 


Tim Madden 
Argonne Lab 





-- 
Henno Kriel 


DSP Engineer 
Digital Back End meerKAT 

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