Hi, Ron, [I meant to send this to the list the first time.]
On May 3, 2013, at 3:57 PM, [email protected] wrote: > I expect > the ADC generating the FPGA clock will be in > sync By definition! > but the other ADC may be 90, 180 or 270 > degrees out of phase with the first ADC. Don't forget 0 degrees out of phase! :-) Even though the clocks can be out of phase, the data from each ADC is clocked into the FPGA using that ADC's clock to ensure proper setup/hold. Internal to the FPGA there is a cross-clock-domain FIFO that transfers the data from ADC1 into the clock domain of ADC0 (which is the main fabric clock domain), so all the data end up on one common clock domain. > Do the yellow blocks sync the ADC's on a ROACH? I don't know. Even if it does sync the two ADCs on one ROACH, it can't sync the ADCs across two ROACHes, so systems that have with more than one ROACH need to deal with the out-of-phase potential anyway. This is usually done by measuring the difference using a common input signal (e.g. noise or the sky). It is quite stable so it only needs to be done once. If you care about this, you will probably also care about line length variations. However you plan on calibrating that can also be used to calibrate the phase offset. The ADC clock phase offset is easier to handle in some ways since it can only be one of several discrete values. Hope this helps, Dave
