Hi, Dan, On May 6, 2013, at 9:23 AM, Dan Werthimer wrote:
> on the yellow blocks i'm familiar with, > if the two adc boards can start up out of sync, > on power up (initialization), one of the adc's (the slave) > is reset as many times as needed until > the slave adc is in sync with master adc. > the fpga uses the clock from the master adc. TinyShell on the iBob used to have start-up software that would sync the ADCs' clocks (at least for the original ADC2x1000-8, aka iADC), but I am not aware of anything equivalent on the ROACH. Has this clock synchronization logic been moved into any ADC yellow block's HDL? Thanks, Dave
