Hi Alex, Lots of questions for you! -- Which adc yellow block are you using, and on which board (Roach/Roach2)? Are you certain nothing has changed in your model between updates (design is still clocked off adc0, adc is still in the right zdok, etc...)? Did you run the matlab script xlUpdateModel() on your design (which supposedly brings all the old system generator blocks up to date)? Which version are you going from / to -- 11.1 -> 14.7, or some other combination? Any suspicious warnings during the compile process?
Cheers, Jack On 5 June 2014 01:27, Alex Zahn <[email protected]> wrote: > Hi all, > > I have a yellowblock for an ADC (made by someone else--I don't know how to > write yellowblocks) meant to clock the design off adc0clk. > > Designs using this yellowblock work fine with ISE 11, but with ISE 14 they > manage to get through compilation successfully, but when running don't seem > to allow the FPGA to receive a clock. > > I suspect there is something wrong with the yellowblock here, but I don't > know where to look or what to look for. Has anyone seen anything like this? > > -Alex > > > >
