Hi Jack, I'm using a yellowblock for a custom ADC on ROACH1; it's not in any of the repositories. The ADC consumes both ZDOK ports, and without changing anything else, just reprogramming from an ISE 11 compiled design to an ISE 14 compiled design appears to cause the problem.
I did not know about xIUpdateModel(). I will try that. I know we were using 11.1 when we got the yellowblock, and last compiled a working design on 11.5. I'm working with 14.7 now. I didn't notice any warnings that looked off, though I should probably look again. Later today I was going to try compiling a minimal model using the yellowblock just to see if that successfully forwards a clock to the FPGA or not. Are there any ways a yellowblock can have issues on a different version of ISE? -Alex On Thu, Jun 5, 2014 at 10:30 AM, Jack Hickish <[email protected]> wrote: > Hi Alex, > > Lots of questions for you! -- > Which adc yellow block are you using, and on which board (Roach/Roach2)? > Are you certain nothing has changed in your model between updates > (design is still clocked off adc0, adc is still in the right zdok, > etc...)? > Did you run the matlab script xlUpdateModel() on your design (which > supposedly brings all the old system generator blocks up to date)? > Which version are you going from / to -- 11.1 -> 14.7, or some other > combination? > Any suspicious warnings during the compile process? > > Cheers, > Jack > > On 5 June 2014 01:27, Alex Zahn <[email protected]> wrote: > > Hi all, > > > > I have a yellowblock for an ADC (made by someone else--I don't know how > to > > write yellowblocks) meant to clock the design off adc0clk. > > > > Designs using this yellowblock work fine with ISE 11, but with ISE 14 > they > > manage to get through compilation successfully, but when running don't > seem > > to allow the FPGA to receive a clock. > > > > I suspect there is something wrong with the yellowblock here, but I don't > > know where to look or what to look for. Has anyone seen anything like > this? > > > > -Alex > > > > > > > > >
