Hi Alex
Just an idea: is this problem by any chance caused by Xilinx dropping
support for the OPB bus in recent ISE versions? If you look around the
CASPER mailing lists, I remember this being quite a big issue around 1-2
years ago.
Maybe your yellow block makes use of this bus?
Regards,
Simon
On 06/05/2014 03:07 PM, Alex Zahn wrote:
Hi all,
A progress update:
I tried to compile a very simple model using the problematic
yellowblock that just flashes an LED. Compilation completes (and the
design does not forward a clock to the FPGA), but I do find some
warning messages I don't understand:
Immediately after the "Running EDK backend" banner comes up, there's a
complaint about a couple of missing files:
 Warning: File
'/home/betacage/roach_designs/adc6x_test/minimal_model/XPS_ROACH_base/implementation/system.bit'
 not found.
 > In gen_xps_files at 663
   In casper_xps>run_Callback at 155
   In casper_xps at 88
   In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
 Warning: File
'/home/betacage/roach_designs/adc6x_test/minimal_model/XPS_ROACH_base/implementation/download.bit'
 not found.
 > In gen_xps_files at 664
  In casper_xps>run_Callback at 155
   In casper_xps at 88
   In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
A little further down after a series of revup messages, this rather
ominous text comes up:
 Computing clock values...
 INFO:EDK - Cannot determine the input clock associated with port :
   infrastructure_inst:epb_clk. Clock DRCs will not be performed
on this core
    and cores connected to it.
 INFO:EDK - Cannot determine the input clock associated with port :
   infrastructure_inst:epb_clk. Clock DRCs will not be performed
on this core
   and cores connected to it.
 INFO:EDK - Cannot determine the input clock associated with port :
   infrastructure_inst:epb_clk. Clock DRCs will not be performed
on this core
    and cores connected to it.
 INFO:EDK - Cannot determine the input clock associated with port :
   infrastructure_inst:epb_clk. Clock DRCs will not be performed
on this core
    and cores connected to it.
 INFO:EDK - Unable to trace clock connectivity for port : adc_clk_out -
  Â
/home/betacage/roach_designs/adc6x_test/minimal_model/XPS_ROACH_base/system.m
   hs line 278. Not performing Clock DRCs
 INFO:EDK - Unable to trace clock connectivity for port : fpga_clk -
  Â
/home/betacage/roach_designs/adc6x_test/minimal_model/XPS_ROACH_base/system.m
    hs line 277. Not performing Clock DRCs
After that, a few blocks of clock related INFOs and warnings that look
similar appear.
I've attached the complete log file for reference. Any ideas on what's
causing this?
-Alex
On Thu, Jun 5, 2014 at 1:55 PM, Alex Zahn <[email protected]
<mailto:[email protected]>> wrote:
Hi Jack,
I'm using a yellowblock for a custom ADC on ROACH1; it's not in
any of the repositories. The ADC consumes both ZDOK ports, and
without changing anything else, just reprogramming from an ISE 11
compiled design to an ISE 14 compiled design appears to cause the
problem.
I did not know about xIUpdateModel(). I will try that. I know we
were using 11.1 when we got the yellowblock, and last compiled a
working design on 11.5. I'm working with 14.7 now.
I didn't notice any warnings that looked off, though I should
probably look again.
Later today I was going to try compiling a minimal model using the
yellowblock just to see if that successfully forwards a clock to
the FPGA or not.
Are there any ways a yellowblock can have issues on a different
version of ISE?
-Alex
On Thu, Jun 5, 2014 at 10:30 AM, Jack Hickish
<[email protected] <mailto:[email protected]>> wrote:
Hi Alex,
Lots of questions for you! --
Which adc yellow block are you using, and on which board
(Roach/Roach2)?
Are you certain nothing has changed in your model between updates
(design is still clocked off adc0, adc is still in the right zdok,
etc...)?
Did you run the matlab script xlUpdateModel() on your design
(which
supposedly brings all the old system generator blocks up to date)?
Which version are you going from / to -- 11.1 -> 14.7, or some
other
combination?
Any suspicious warnings during the compile process?
Cheers,
Jack
On 5 June 2014 01:27, Alex Zahn <[email protected]
<mailto:[email protected]>> wrote:
> Hi all,
>
> I have a yellowblock for an ADC (made by someone else--I
don't know how to
> write yellowblocks) meant to clock the design off adc0clk.
>
> Designs using this yellowblock work fine with ISE 11, but
with ISE 14 they
> manage to get through compilation successfully, but when
running don't seem
> to allow the FPGA to receive a clock.
>
> I suspect there is something wrong with the yellowblock
here, but I don't
> know where to look or what to look for. Has anyone seen
anything like this?
>
> -Alex
>
>
>
>
