hi Rolando, the quad adc outputs one sample per FPGA clock, so your correlator will need to use an FFT with real input, complex output, 1 real input sample per clock.
I think (but I'm not sure), the *fft_biplex_real_2x block does* *two real to complex ffts, so you'll need* *two of these blocks to compute four* *fft's on four inputs.* *best wishes,* *dan* On Sun, Aug 31, 2014 at 10:00 AM, Rolando Paz <[email protected]> wrote: > Could someone please explain why the QUADC designs use only the > fft_bliplex_real_2x block? > > Why the fft_biplex_real_2x block uses more resources than the > fft_wideband_real block? > > Best Regards > > Rolando Paz >
