Hi Rolando
Now, I need to understand the equalizer block.
After the FFT the size of each data sample has grown. Many astronomical signals have a frequency spectrum that is related to white noise. This means that each frequency channel sample is about the same size. So we don't need lots of bits for each sample as the smallest number we need is nearly the same size as the biggest. Channels with large numbers at this point are often RFI which we will not use.
We can save FPGA resources and bandwidth if we make the numbers smaller before processing the data further. If we just took the top (most significant) bits, we might lose some data, this depends on the power of the signal we are looking at. So we boost the signal by multiplying it with a number so that the result lies in the most significant bits before throwing the other bits away. We may want each channel (or a group of channels next to each other) from the FFT to be multiplied by a different number, it depends on what our signal looks like and what our system has done to the signal.
How I can know if the equalizer block is working correctly?
A good way to start would be to simulate using data that has similar characteristics to what you expect from the signal you will look at. Get a noise signal which uses the same number of bits when sampled by the ADC and put that into your system. Then put down some Scopes and look at what happens in the signal chain. If your equalizer values are too small, then you will see zeros going to the xengine, if the values are too big, then there will just be saturated (the maximum value) values going to the xengine.
On a real system, try changing the values to something small so that the final values are 0 or very small, then slowly increase the values until you see the outputs stop increasing.
I have also doubts about the config file. This is the part with which I program the IBOB: [equalisation] #Perform automatic equalization (=1) or set to fixed EQ_poly values (=0) auto_eq = 0 #Number of equalization blocks, include an eq_poly_x entry for each block eq_blocks = 4 #Number of equalization channels per equalization block eq_chans = 64 #Starting point for auto-equalization or values for manual eq programming. #One line entry per antenna. Item is a list of polynomial coefficients. #Eg, #EQ_poly_0 = 10, 30 ,40 #corresponds to 10 + 30x^2 + 40x^4 eq_poly_0 = 300 eq_poly_1 = 300 eq_poly_2 = 300 eq_poly_3 = 300 Do you know what does this?
You should look in the code and the model for where these values are used and try to understand what is happening. Getting these equalization values right is important and different experiments will require different values. It is very important to really understand what is happening.
You should also simulate using the fft_biplex_real_2x block and understand how the data comes out.
Good luck Andrew
2014-08-31 16:50 GMT-06:00 Dan Werthimer <[email protected] <mailto:[email protected]>>: On Sun, Aug 31, 2014 at 3:40 PM, Rolando Paz <[email protected] <mailto:[email protected]>> wrote: Hi again... I'm using a IBOB-QUADC, the FPGA clock rate is 200MHz, and QUADC clock rate is 200 MHz. The size of PFB and FFT is 2^11 pnts, and that means that I have 1024 channels for each of the four inputs of the QUADC, is this correct? yes, that's correct: 2048 real points in and out of the PFB FIR, as well as into the FFT. 1024 complex points out of the FFT. My correlation block is called "xengine4", and within are 6 cross-correlations and 4 autocorrelations. That means that I have 16 BRAM in the correlator's design. For each BRAM I use a "vacc_32bit" block . If the design can handle four real independent streams, as we have discussed, Does this means that I should set each "vacc_32bit" block with 1024 channels? yes. Best Regards Rolando Paz 2014-08-31 11:33 GMT-06:00 Dan Werthimer <[email protected] <mailto:[email protected]>>: i think the FFT biplex real 2x block can compute real to complex FFT's on 4, 8, 12, 16.... inputs, depending on how you set the "Number simultaneous inputs" parameter. best wishes, dan On Sun, Aug 31, 2014 at 10:26 AM, Rolando Paz <[email protected] <mailto:[email protected]>> wrote: Hi Dan Now I understand :-) It's very different this: 4 time samples in parallel (fft_wideband_real) 4 real streams (fft_biplex_real_2x) Casper's website says (https://casper.berkeley.edu/wiki/Fft_biplex_real_2x): ...Thus, a biplex core (which can do 2 complex FFTs) can transform 4 real streams. Twiddle factor, and other logic sharing, allows multiples of 4 input streams to be processed simultaneously with minimal resource increases... Does this mean that I only need a single block? Best Regards Rolando Paz 2014-08-31 11:06 GMT-06:00 Dan Werthimer <[email protected] <mailto:[email protected]>>: hi Rolando, the quad adc outputs one sample per FPGA clock, so your correlator will need to use an FFT with real input, complex output, 1 real input sample per clock. I think (but I'm not sure), the *fft_biplex_real_2x block does* *two real to complex ffts, so you'll need* *two of these blocks to compute four* *fft's on four inputs.* *** * *best wishes,* * * *dan* On Sun, Aug 31, 2014 at 10:00 AM, Rolando Paz <[email protected] <mailto:[email protected]>> wrote: Could someone please explain why the QUADC designs use only the fft_bliplex_real_2x block? Why the fft_biplex_real_2x block uses more resources than the fft_wideband_real block? Best Regards Rolando Paz
