Hi Michael, Which exact mlib_devel commit from which fork are you using?
I believe this was fixed in commit sma-wideband/mlib_devel@404989f on June 27, 2014. See the github link here: https://github.com/sma-wideband/mlib_devel/commit/404989f It's possible this somehow did not make it to the repo you are using (hasn't been merged in yet). Thanks, Rurik On Thu, Aug 13, 2015 at 1:49 PM, Michael D'Cruze < [email protected]> wrote: > Hello, > > > > I’m getting an error on compiling a spectrometer design which I’m having > trouble understanding. The following appears in the command line interface: > > > > ERROR:PhysDesignRules:2506 - Incorrect placement for a BUFR component. BUFR > > mdl_bbox_quant_asiaa_adc5g/mdl_bbox_quant_asiaa_adc5g/DIVBUF in clock > region CLOCKREGION_X0Y7 is driven by a CCIO > > adc0clk_p in clock region CLOCKREGION_X0Y5. The BUFR should be placed > in the same clock region as the CCIO or the > > CLOCK_DEDICATED_ROUTE constraint should be used on the net > > <mdl_bbox_quant_asiaa_adc5g/mdl_bbox_quant_asiaa_adc5g/adc_clk>. > > ERROR:Pack:1642 - Errors in physical DRC. > > > > It reads to me as if there’s something wrong with the ADC block > internally, but as I’ve got a very recent commit I can’t see how that could > be, especially given the number of people using this block… > > > > For completeness, I’m using a 2048 MHz ADC clock in single channel mode > (for 2048 MHz input bandwidth) and have set the fabric clock to 4096/16=256 > MHz running off the ADC clock. The actual ADC is in ZDOK0. > > > > Any help would be greatly appreciated; I can only see one error similar to > this on the mail archive and it seemed to have been fixed in a subsequent > mlib_devel commit. > > > > Thanks > > Michael >
