Hi Jack, Primiani, That seems to have worked – thanks.
Is this particular branch a beta-test version for fixes before they become mainstream? Cheers Michael From: Jack Hickish [mailto:[email protected]] Sent: 13 August 2015 19:06 To: Michael D'Cruze; [email protected] Subject: Re: [casper] 5GS/s ADC compile errors Hi Michael, This is fixed by commit 404989f. It's in the casper-astro-soak-test branch of https://github.com/casper-astro/mlib_devel There's a bunch of other fixes in this branch, so I would suggest using it. At some point in the hopefully near future it will become the standard casper-astro master branch. Cheers, Jack On Thu, 13 Aug 2015 at 10:50 Michael D'Cruze <[email protected]<mailto:[email protected]>> wrote: Hello, I’m getting an error on compiling a spectrometer design which I’m having trouble understanding. The following appears in the command line interface: ERROR:PhysDesignRules:2506 - Incorrect placement for a BUFR component. BUFR mdl_bbox_quant_asiaa_adc5g/mdl_bbox_quant_asiaa_adc5g/DIVBUF in clock region CLOCKREGION_X0Y7 is driven by a CCIO adc0clk_p in clock region CLOCKREGION_X0Y5. The BUFR should be placed in the same clock region as the CCIO or the CLOCK_DEDICATED_ROUTE constraint should be used on the net <mdl_bbox_quant_asiaa_adc5g/mdl_bbox_quant_asiaa_adc5g/adc_clk>. ERROR:Pack:1642 - Errors in physical DRC. It reads to me as if there’s something wrong with the ADC block internally, but as I’ve got a very recent commit I can’t see how that could be, especially given the number of people using this block… For completeness, I’m using a 2048 MHz ADC clock in single channel mode (for 2048 MHz input bandwidth) and have set the fabric clock to 4096/16=256 MHz running off the ADC clock. The actual ADC is in ZDOK0. Any help would be greatly appreciated; I can only see one error similar to this on the mail archive and it seemed to have been fixed in a subsequent mlib_devel commit. Thanks Michael
