Hi Mike, I know that JP did some great work on the DDR3 controller on ROACH2 you can find the pcores here: https://github.com/ska-sa/mlib_devel/tree/master/xps_base/XPS_ROACH2_base/pcores
This works, but just doesn't have a CPU interface, which you might/might not need. Although, I seem to remember Rurik and Laura adding a CPU interface at some stage. I tried briefly to get it working on the SKA-SA repository and hit some OPB address mapping issues. We didn't have much time and didn't need it, so never got around to completing it. The one option is to use the CPU interface from the ROACH1 pcores, you would just have to change the bus widths and the memory mapping. Hope this puts you on the right path. Regards Wesley Wesley New South African SKA Project +2721 506 7300 www.ska.ac.za On Thu, Apr 7, 2016 at 12:23 PM, Mike Movius <[email protected]> wrote: > > Hi All, > > Does anyone know if there has been progress made on a CPU interface for > the DDR3 on the Roach2? I have seen mention of some effort by various > parties in the mail archive and was wondering if there is a mlib_devel repo > somewhere that I might use. Even a partial implementation would help as a > starting point. Thanks, MM. > > > Please consider the environment before printing this e-mail > > View the Reutech Radar System online disclaimer at > http://www.rrs.co.za/links/E-maildisclaimer.asp >
