Sorry, that is page 49 and 50. Wesley New South African SKA Project +2721 506 7300 www.ska.ac.za
On Wed, Jun 15, 2016 at 11:25 AM, Wesley New <[email protected]> wrote: > Hi Mike, > > This one got me a while back. I think you need to change the style option > in your mpd file to hdl. See page 47 of this document. > http://www.xilinx.com/support/documentation/sw_manuals/edk10_psf_rm.pdf > > Regards > > Wesley > > > Wesley New > South African SKA Project > +2721 506 7300 > www.ska.ac.za > > > > On Wed, Jun 15, 2016 at 10:30 AM, Mike Movius <[email protected]> wrote: > >> >> Hi all, >> >> I have recently implemented a cpu interface for the ddr3 on the roach2. I >> am cleaning up the pcore in preparation to supply it to ska-sa for >> commiting into their repository after they vet the design. I based the >> design on the dram pcore for roach one but re-implemented the arbiter. I no >> longer need the read_history_fifo.ngc that was previously used in the >> arbiter but I can’t delete it from the pcore \netlist directory without my >> compile failing. I know I need to do something with the \data\.bbd file. I >> tried deleting the file and also just using an empty file as there are no >> coregen .ngc files required but neither worked. I know I am missing >> something small. Any help appreciated. Thanks, MM. >> >> >> Please consider the environment before printing this e-mail >> >> View the Reutech Radar System online disclaimer at >> http://www.rrs.co.za/links/E-maildisclaimer.asp >> > >
