Howdy, If you go to the opb_opb_lite pcore directory you'll find a file data/opb_opb_lite_something.mpd. This should have a line indicating supported platforms - add VIRTEX6 and you should be good to go. You might have to do this for some of the other deprecated pcores too. The currently linked pcores on the Casper wiki should already have this fixed - let me know if this isn't the case.
Jack On Tue, 17 May 2016, 02:58 Mike Movius, <[email protected]> wrote: > > Hi All, > > I am attempting to add a cpu interface the roach2 ddr3 yellow block. JP > has given me a model to test with but I am having problems getting it to > compile. The problem seems to be related to the number of opb buses > required for the brams in the snapshot blocks. If I comment a number of > them out things are fine but above a certain number I get the following > warning and error: > > > > WARNING:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: > > ddr3_tst_r2_2x_snapshot_err_tx_data_bram - Superseded core for > architecture > > 'virtex6sx' - d:\temp\ddr3_tst_r2_2x\XPS_ROACH2_base\system.mhs line > 910 > > ERROR:EDK - IPNAME: opb_opb_lite, INSTANCE: opb2opb_bridge_opb1 - not > supported > > for architecture 'virtex6sx' - > > d:\temp\ddr3_tst_r2_2x\XPS_ROACH2_base\system.mhs line 954 > > ERROR:EDK - while loading XMP file > > > > I see that this caused by the following entry in the system.mhs file > > > > # OPB to OPB bridge added at 0x1080000 > > BEGIN opb_v20 > > PARAMETER INSTANCE = opb1 > > PARAMETER HW_VER = 1.10.c > > PARAMETER C_EXT_RESET_HIGH = 1 > > PORT SYS_Rst = sys_reset > > PORT OPB_Clk = epb_clk > > END > > > > BEGIN opb_opb_lite > > PARAMETER INSTANCE = opb2opb_bridge_opb1 > > PARAMETER HW_VER = 1.00.a > > PARAMETER C_NUM_DECODES = 1 > > PARAMETER C_DEC0_BASEADDR = 0x01080000 > > PARAMETER C_DEC0_HIGHADDR = 0x010FFFFF > > BUS_INTERFACE SOPB = opb0 > > BUS_INTERFACE MOPB = opb1 > > PORT MOPB_Clk = epb_clk > > PORT SOPB_Clk = epb_clk > > END > > > > I have confirmed that the opb_opb_lite pcore is in my base\pcore directory > and I am using ISE 14.7. Any help appreciated. Thanks, MM. > > *From:* Wesley New [mailto:[email protected]] > *Sent:* 07 April 2016 01:21 PM > *To:* Mike Movius > *Cc:* [email protected] > *Subject:* Re: [casper] ddr3 cpu interface for roach2 > > > > Hi Mike, > > > > I know that JP did some great work on the DDR3 controller on ROACH2 you > can find the pcores here: > https://github.com/ska-sa/mlib_devel/tree/master/xps_base/XPS_ROACH2_base/pcores > > > > This works, but just doesn't have a CPU interface, which you might/might > not need. Although, I seem to remember Rurik and Laura adding a CPU > interface at some stage. I tried briefly to get it working on the SKA-SA > repository and hit some OPB address mapping issues. We didn't have much > time and didn't need it, so never got around to completing it. The one > option is to use the CPU interface from the ROACH1 pcores, you would just > have to change the bus widths and the memory mapping. > > > > Hope this puts you on the right path. > > > > Regards > > > > Wesley > > > Wesley New > > South African SKA Project > > +2721 506 7300 > > www.ska.ac.za > > > > > > > > On Thu, Apr 7, 2016 at 12:23 PM, Mike Movius <[email protected]> wrote: > > > > Hi All, > > Does anyone know if there has been progress made on a CPU interface for > the DDR3 on the Roach2? I have seen mention of some effort by various > parties in the mail archive and was wondering if there is a mlib_devel repo > somewhere that I might use. Even a partial implementation would help as a > starting point. Thanks, MM. > > > > Please consider the environment before printing this e-mail > > > > View the Reutech Radar System online disclaimer at > > http://www.rrs.co.za/links/E-maildisclaimer.asp > > > > > Please consider the environment before printing this e-mail > > View the Reutech Radar System online disclaimer at > http://www.rrs.co.za/links/E-maildisclaimer.asp >
