Hi Paul

I had to try the following from my side:

1. I cloned the repos from casper-astro mlib_devel
https://github.com/casper-astro/mlib_devel/tree/devel [devel branch] and
https://github.com/casper-astro/tutorials_devel [master branch]
2. I successfully compiled the first tutorial
https://github.com/casper-astro/tutorials_devel/tree/master/red_pitaya/tut_intro
and
programmed the red pitaya - tested all good.
3. I successfully compiled the second tutorial
https://github.com/casper-astro/tutorials_devel/tree/master/red_pitaya/tut_adc_dac
and
programmed the red pitaya - tested all good.
4. I ran the tut_spec.py script at
https://github.com/casper-astro/tutorials_devel/tree/master/red_pitaya/tut_spec
using
the tut_spec.fpg file. No issues.
5. I ran the tut_spec.py script at
https://github.com/casper-astro/tutorials_devel/tree/master/red_pitaya/tut_spec
using
the fpg file that I compiled from tut_spec.slx. No issues.

I am using Matlab 2018a and Vivado 2019.1. Can you refine which ones you
use particularly eg 2018a or 2018b and 2019.1 or 2019.2. I am not sure
about compatibility, though.

It seems there is no problem with the design files in the repos.

What do you get if you run: casperfga.__version__

Further investigations will follow.

Thanks
Mathews






On Fri, Aug 28, 2020 at 8:50 AM Adam Isaacson <[email protected]> wrote:

> Hi Paul,
>
> Thanks, I will investigate further and get back to you.
>
> Kind regards,
>
> Adam Isaacson
> South African Radio Astronomy Observatory (SARAO)
> Hardware Manager
> Cell: (+27) 825639602
> Tel:  (+27) 215067300
> email: [email protected]
>
>
>
> On Thu, Aug 27, 2020 at 10:49 PM Paul Akumu <[email protected]> wrote:
>
>> Hi Adam,
>>
>> I have tried the recommended repos but the error still persists.
>>
>> Kind regards,
>> Paul.
>>
>> On Thu, Aug 27, 2020 at 11:00 AM Adam Isaacson <[email protected]>
>> wrote:
>>
>>> Hi Paul,
>>>
>>> Thanks for confirming. Please can you try the latest commits and
>>> following repos:
>>>
>>> 1) mlib_devel - https://github.com/ska-sa/mlib_devel
>>> <https://github.com/ska-sa/mlib_devel> (devel branch)
>>> 2) casperfpga - https://github.com/ska-sa/casperfpga (devel branch)
>>>
>>> These repos contain the latest Red Pitaya fixes. If the problem still
>>> persists then I will investigate further. I just want to make sure that we
>>> have merged all the relevant fixes in the casper-astro repo from the ska-sa
>>> repo.
>>>
>>> Kind regards,
>>>
>>> Adam Isaacson
>>> South African Radio Astronomy Observatory (SARAO)
>>> Hardware Manager
>>> Cell: (+27) 825639602
>>> Tel:  (+27) 215067300
>>> email: [email protected]
>>>
>>>
>>>
>>> On Wed, Aug 26, 2020 at 8:39 PM Paul Akumu <[email protected]> wrote:
>>>
>>>> Hi Adam,
>>>>
>>>> Yes, I built the slx files and generated the fpg files for the first
>>>> two tutorials.
>>>>
>>>> For the third tutorial, I first opened the slx file in Simulink and
>>>> compiled it but got an error when I tried to upload and program. Then I
>>>> tried updating the model as described under "Updating an Existing Toolfow
>>>> Installation" using update_casper_blocks(bdroot) before compiling
>>>> again but got the same error report. Finally, I tried using the fpg file
>>>> provided which also resulted in the same error.
>>>>
>>>> Thanks,
>>>> Paul.
>>>>
>>>>
>>>>
>>>>
>>>> <https://www.avast.com/sig-email?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail&utm_term=icon>
>>>>  Virus-free.
>>>> www.avast.com
>>>> <https://www.avast.com/sig-email?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail&utm_term=link>
>>>> <#m_5257118673740282965_m_-3441388826180357240_m_-3334835703352447321_m_5458899884828230806_m_6900430746832513320_m_497581565406995344_m_7518126369254170950_DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
>>>>
>>>> On Wed, Aug 26, 2020 at 3:49 PM Adam Isaacson <[email protected]>
>>>> wrote:
>>>>
>>>>> Hi Paul,
>>>>>
>>>>> Thanks for your email. It looks like your mlib_devel and casperfpga
>>>>> version are fairly recent and contain the BRAM 32 bit fixes that we made.
>>>>> It seems I committed this particular fpg file 9 months ago, so it might 
>>>>> not
>>>>> of contained all these fixes then. I am quite certain it was working for
>>>>> me, but maybe I committed the incorrect file at the time. You say the 
>>>>> first
>>>>> two tutorials were successful and I know the second tutorial has a
>>>>> snapshot, so your build environment must work. I am assuming you build the
>>>>> slx files and generated the fpg files for the first two tuts, of course.
>>>>> Correct me if wrong!
>>>>>
>>>>> Please try and rebuild the spectrometer slx file and test the fpg
>>>>> generated file. Let me know if you get the same issue. If you don't then I
>>>>> must have checked a suspect fpg file in this repo and we can easily fix
>>>>> that, if that is the case.
>>>>>
>>>>> Kind regards,
>>>>>
>>>>> Adam Isaacson
>>>>> South African Radio Astronomy Observatory (SARAO)
>>>>> Hardware Manager
>>>>> Cell: (+27) 825639602
>>>>> Tel:  (+27) 215067300
>>>>> email: [email protected]
>>>>>
>>>>>
>>>>>
>>>>> On Mon, Aug 24, 2020 at 10:52 PM Paul Akumu <[email protected]>
>>>>> wrote:
>>>>>
>>>>>> Hello,
>>>>>>
>>>>>> I am new to the Toolfow and I have been following the Red Pitaya
>>>>>> tutorials. I have Matlab 2018 and Vivado 2019 installed. I was able to
>>>>>> follow the first two tutorials which compiled and uploaded via casperfpga
>>>>>> successfully. When following the wide band spectrometer tutorial I tried 
>>>>>> to
>>>>>> program the red Pitaya with the fpg file provided for the tutorial
>>>>>> here
>>>>>> <https://github.com/casper-astro/tutorials_devel/tree/master/red_pitaya/tut_spec>,
>>>>>> but got the following response/error;
>>>>>>
>>>>>> Connecting to Red Pitaya: 192.168.200.151
>>>>>> Uploading: tut_spec.fpg
>>>>>> These are the devices in your design ...
>>>>>> ['acc_cnt', 'acc_len', 'accum0_snap_ss_bram', 'accum0_snap_ss_ctrl',
>>>>>> 'accum0_snap_ss_status', 'accum1_snap_ss_bram', 'accum1_snap_ss_ctrl',
>>>>>> 'accum1_snap_ss_status', 'accumdat_snap_ss_bram', 
>>>>>> 'accumdat_snap_ss_ctrl',
>>>>>> 'accumdat_snap_ss_status', 'adc_dv', 'adc_sample_cnt',
>>>>>> 'adc_voltage_snap_ss_bram', 'adc_voltage_snap_ss_ctrl',
>>>>>> 'adc_voltage_snap_ss_status', 'fft_sync_inc0', 'fft_sync_inc1',
>>>>>> 'reg_cntrl', 'snap_gap', 'sync_cnt', 'sync_reg', 'sys_block',
>>>>>> 'sys_board_id', 'sys_clkcounter', 'sys_rev', 'sys_rev_rcs',
>>>>>> 'sys_scratchpad']
>>>>>> Traceback (most recent call last):
>>>>>>   File "tut_spec.py", line 38, in <module>
>>>>>>     spec0=fpga.snapshots.accum0_snap_ss.read(arm=False)['data']
>>>>>>   File "/usr/local/lib/python2.7/dist-packages/casperfpga/snap.py",
>>>>>> line 227, in read
>>>>>>     rawdata, rawtime = self.read_raw(**kwargs)
>>>>>>   File "/usr/local/lib/python2.7/dist-packages/casperfpga/snap.py",
>>>>>> line 333, in read_raw
>>>>>>     bram_dmp['length'] / (self.width_bits / 8)))
>>>>>> RuntimeError: accum0_snap_ss.read_uint() - expected 16384 bytes, got
>>>>>> 32
>>>>>>
>>>>>> I also tried compiling the .slx file and got the same error while
>>>>>> trying to upload and program.
>>>>>>
>>>>>> The version of casperfpga and mlib_devel are as follows:
>>>>>> mlib_devel commit id = a9e87d994cf5f512fa0ea555ec7495d8dedc0855
>>>>>> caspserfpga commit id = c2258ea014340a7376d504e7128198ed2cfa5442
>>>>>>
>>>>>> What could be the problem?
>>>>>>
>>>>>> Thanks,
>>>>>> Paul.
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
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>>>>>>
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>>>>
>>>>
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