Hi Stefan,

Sounds fun! Depending what exactly you need to mess with you might
need to dig around a bit, but as a starting point -- this is where the
main RP infrastructure is instantiated:

https://github.com/casper-astro/mlib_devel/blob/390b7c262f0f7418c45bfb98f5aa969a0a432564/jasper_library/yellow_blocks/red_pitaya.py#L75

That python file also controls what external pins get hooked up where,
so you might have to change various bits of it.

which instantiates the sources

https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/hdl_sources/infrastructure/red_pitaya.v
and
https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/hdl_sources/infrastructure/red_pitaya.tcl

Does modifying these get you where you need to be?

Of course, there is probably a  "proper" way to do this, which might
involve doing something like adding a "sata_clk" input to the Red
Pitaya platform block "clock sources" options, and carrying the
parameterization through the build chain.

For starters, you could also open the
<build_directory>/myproj/myproj.xpr vivado project and modify it as
per the guide you linked, rather than trying to mess with the toolflow
straight out the gate.

I'm not wildly familiar with the RP platform, so maybe someone else
has more wisdom to share.

Cheers
Jack

On Wed, 3 Nov 2021 at 11:34, Haensel, Stefan <[email protected]> wrote:
>
> Hello,
>
> I try to synchronize several Red Pitayas (RPs) to the same clock. For that RP 
> has a SATA connector to hand over the clock to the next RP as written here:
> https://www.koheron.com/blog/2016/11/29/red-pitaya-cluster
>
> For that I need to change the PLL of the slave RPs. Is there somewhere a 
> documentation, which describes how to change IP blocks? How is the PLL 
> generated right now with the CASPER workflow?
>
> Is it possible to open a PLL wizard and just change the settings or can I 
> supply a variable, that controls the phase shift of a mixed-mode clock?
>
> Thanks,
> Stefan
>
>
>
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