If you can get a Vivado project with the changes you need, it shouldn't
be too hard for someone familiar with the toolflow to walk you through
propagating these back to the auto-generation scripts. The slack
channel Adam linked is a good place to seek help with that.

Cheers

Jack

On Wed, 3 Nov 2021 at 14:39, Adam Isaacson <[email protected]> wrote:
>
> Hi Stefan,
>
> Yes, that is correct. The changes that you make to myproj,xpr will be 
> overwritten should you rerun the toolflow. However, if you make the changes 
> in the file locations that Jack and I showed then it won't. Good luck!
>
> Kind regards,
>
> Adam
>
> On Wed, Nov 3, 2021 at 4:23 PM Haensel, Stefan <[email protected]> 
> wrote:
>>
>> Hi Adam and hi Jack,
>>
>>
>>
>> Adding the PINs and changing the input of the MMCM in the red_pitaya.v file 
>> sounds doable.
>>
>> Maybe I start with the “myproj.xpr” file. But I assume, that the changes in 
>> the myproj.xpr file will not exists anymore once I rerun the workflow.
>>
>>
>>
>> It will talk some time until I will get a running project, but I will let 
>> you know, how I solved it or ask further questions, if I have trouble.
>>
>>
>>
>> Best Regards,
>>
>> Stefan
>>
>>
>>
>>
>>
>> Von: Adam Isaacson <[email protected]>
>> Gesendet: Mittwoch, 3. November 2021 14:03
>> An: Casper Lists <[email protected]>
>> Betreff: Re: [casper] Synchronize a cluster of Red Pitayas using CASPER
>>
>>
>>
>> Hi Jack and Stefan,
>>
>>
>>
>> I am not sure if we ever used the SATA connector or rather my memory thinks 
>> not. On top of what Jack has suggested then you will also need to add the 
>> SATA pin outs to the platform yaml file below - you will need to add the 
>> pins of choice here, otherwise the generated top.v file won't connect the 
>> top level pins to the infrastructure:
>>
>>
>>
>> https://github.com/casper-astro/mlib_devel/blob/390b7c262f0f7418c45bfb98f5aa969a0a432564/jasper_library/platforms/red_pitaya_14.yaml
>>
>>
>>
>> I assume you are using the Red Pitaya 14 bit DAC and ADC since you have the 
>> version with the SATA interface? If you are using anything else then there 
>> will be other modifications to be made e.g. making provision for the 16 bit 
>> ADC.
>>
>>
>>
>> This may also help - explanation of the Red Pitaya hardware:
>>
>>
>>
>> https://github.com/casper-astro/casper-hardware/blob/master/FPGA_Hosts/RED_PITAYA/README.md
>>
>>
>>
>> These are definitely the main files you will need to change the MMCM 
>> parameters to produce a clock frequency of your choice and route out the 
>> synchronised clock. Good luck and feel free to use our slack group for 
>> support - invite below!
>>
>>
>>
>> https://join.slack.com/t/casper-astro/shared_invite/zt-wmdj9maf-Mlp_98lQtzjA1n1Be~5oOA
>>
>>
>>
>> Kind regards,
>>
>>
>>
>> Adam
>>
>>
>>
>> On Wed, Nov 3, 2021 at 2:39 PM Jack Hickish <[email protected]> wrote:
>>
>> Hi Stefan,
>>
>> Sounds fun! Depending what exactly you need to mess with you might
>> need to dig around a bit, but as a starting point -- this is where the
>> main RP infrastructure is instantiated:
>>
>> https://github.com/casper-astro/mlib_devel/blob/390b7c262f0f7418c45bfb98f5aa969a0a432564/jasper_library/yellow_blocks/red_pitaya.py#L75
>>
>> That python file also controls what external pins get hooked up where,
>> so you might have to change various bits of it.
>>
>> which instantiates the sources
>>
>> https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/hdl_sources/infrastructure/red_pitaya.v
>> and
>> https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/hdl_sources/infrastructure/red_pitaya.tcl
>>
>> Does modifying these get you where you need to be?
>>
>> Of course, there is probably a  "proper" way to do this, which might
>> involve doing something like adding a "sata_clk" input to the Red
>> Pitaya platform block "clock sources" options, and carrying the
>> parameterization through the build chain.
>>
>> For starters, you could also open the
>> <build_directory>/myproj/myproj.xpr vivado project and modify it as
>> per the guide you linked, rather than trying to mess with the toolflow
>> straight out the gate.
>>
>> I'm not wildly familiar with the RP platform, so maybe someone else
>> has more wisdom to share.
>>
>> Cheers
>> Jack
>>
>> On Wed, 3 Nov 2021 at 11:34, Haensel, Stefan <[email protected]> 
>> wrote:
>> >
>> > Hello,
>> >
>> > I try to synchronize several Red Pitayas (RPs) to the same clock. For that 
>> > RP has a SATA connector to hand over the clock to the next RP as written 
>> > here:
>> > https://www.koheron.com/blog/2016/11/29/red-pitaya-cluster
>> >
>> > For that I need to change the PLL of the slave RPs. Is there somewhere a 
>> > documentation, which describes how to change IP blocks? How is the PLL 
>> > generated right now with the CASPER workflow?
>> >
>> > Is it possible to open a PLL wizard and just change the settings or can I 
>> > supply a variable, that controls the phase shift of a mixed-mode clock?
>> >
>> > Thanks,
>> > Stefan
>> >
>> >
>> >
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