Hi Adam and hi Jack, Adding the PINs and changing the input of the MMCM in the red_pitaya.v file sounds doable. Maybe I start with the "myproj.xpr" file. But I assume, that the changes in the myproj.xpr file will not exists anymore once I rerun the workflow.
It will talk some time until I will get a running project, but I will let you know, how I solved it or ask further questions, if I have trouble. Best Regards, Stefan Von: Adam Isaacson <[email protected]> Gesendet: Mittwoch, 3. November 2021 14:03 An: Casper Lists <[email protected]> Betreff: Re: [casper] Synchronize a cluster of Red Pitayas using CASPER Hi Jack and Stefan, I am not sure if we ever used the SATA connector or rather my memory thinks not. On top of what Jack has suggested then you will also need to add the SATA pin outs to the platform yaml file below - you will need to add the pins of choice here, otherwise the generated top.v file won't connect the top level pins to the infrastructure: https://github.com/casper-astro/mlib_devel/blob/390b7c262f0f7418c45bfb98f5aa969a0a432564/jasper_library/platforms/red_pitaya_14.yaml<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fcasper-astro%2Fmlib_devel%2Fblob%2F390b7c262f0f7418c45bfb98f5aa969a0a432564%2Fjasper_library%2Fplatforms%2Fred_pitaya_14.yaml&data=04%7C01%7Cstefan.haensel%40siemens.com%7C777deb4e80334e267d8c08d99ec991e9%7C38ae3bcd95794fd4addab42e1495d55a%7C1%7C0%7C637715412329167059%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=rOW94tleZBFhHApyGgVHqbbhAF%2FNymvngrdtlRqV8Mc%3D&reserved=0> I assume you are using the Red Pitaya 14 bit DAC and ADC since you have the version with the SATA interface? If you are using anything else then there will be other modifications to be made e.g. making provision for the 16 bit ADC. This may also help - explanation of the Red Pitaya hardware: https://github.com/casper-astro/casper-hardware/blob/master/FPGA_Hosts/RED_PITAYA/README.md<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fcasper-astro%2Fcasper-hardware%2Fblob%2Fmaster%2FFPGA_Hosts%2FRED_PITAYA%2FREADME.md&data=04%7C01%7Cstefan.haensel%40siemens.com%7C777deb4e80334e267d8c08d99ec991e9%7C38ae3bcd95794fd4addab42e1495d55a%7C1%7C0%7C637715412329167059%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=9Wls1uj4%2BR0X%2B5mxPcdfsSCNyIObZXe38Rcghnihlgc%3D&reserved=0> These are definitely the main files you will need to change the MMCM parameters to produce a clock frequency of your choice and route out the synchronised clock. Good luck and feel free to use our slack group for support - invite below! https://join.slack.com/t/casper-astro/shared_invite/zt-wmdj9maf-Mlp_98lQtzjA1n1Be~5oOA<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fjoin.slack.com%2Ft%2Fcasper-astro%2Fshared_invite%2Fzt-wmdj9maf-Mlp_98lQtzjA1n1Be~5oOA&data=04%7C01%7Cstefan.haensel%40siemens.com%7C777deb4e80334e267d8c08d99ec991e9%7C38ae3bcd95794fd4addab42e1495d55a%7C1%7C0%7C637715412329177019%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=bOFtwxYIAuAuLtxi54a0yPP13dwCpzwiDEONJfFyEzo%3D&reserved=0> Kind regards, Adam On Wed, Nov 3, 2021 at 2:39 PM Jack Hickish <[email protected]<mailto:[email protected]>> wrote: Hi Stefan, Sounds fun! Depending what exactly you need to mess with you might need to dig around a bit, but as a starting point -- this is where the main RP infrastructure is instantiated: https://github.com/casper-astro/mlib_devel/blob/390b7c262f0f7418c45bfb98f5aa969a0a432564/jasper_library/yellow_blocks/red_pitaya.py#L75<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fcasper-astro%2Fmlib_devel%2Fblob%2F390b7c262f0f7418c45bfb98f5aa969a0a432564%2Fjasper_library%2Fyellow_blocks%2Fred_pitaya.py%23L75&data=04%7C01%7Cstefan.haensel%40siemens.com%7C777deb4e80334e267d8c08d99ec991e9%7C38ae3bcd95794fd4addab42e1495d55a%7C1%7C0%7C637715412329186968%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=btWXGRMMY4U3VDlesWrNUuuOYMF2aw0LT1oxfUiiKXk%3D&reserved=0> That python file also controls what external pins get hooked up where, so you might have to change various bits of it. which instantiates the sources https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/hdl_sources/infrastructure/red_pitaya.v<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fcasper-astro%2Fmlib_devel%2Fblob%2Fmaster%2Fjasper_library%2Fhdl_sources%2Finfrastructure%2Fred_pitaya.v&data=04%7C01%7Cstefan.haensel%40siemens.com%7C777deb4e80334e267d8c08d99ec991e9%7C38ae3bcd95794fd4addab42e1495d55a%7C1%7C0%7C637715412329186968%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=v8XOxTcRBNnKEy2P3GkqtuLcooJ7kFmRxuiRUDPefpI%3D&reserved=0> and https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/hdl_sources/infrastructure/red_pitaya.tcl<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fcasper-astro%2Fmlib_devel%2Fblob%2Fmaster%2Fjasper_library%2Fhdl_sources%2Finfrastructure%2Fred_pitaya.tcl&data=04%7C01%7Cstefan.haensel%40siemens.com%7C777deb4e80334e267d8c08d99ec991e9%7C38ae3bcd95794fd4addab42e1495d55a%7C1%7C0%7C637715412329196927%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=0quM9uPWt5uBqXr1gkmxBdg4QExSqwsemBdtBE2KiXc%3D&reserved=0> Does modifying these get you where you need to be? Of course, there is probably a "proper" way to do this, which might involve doing something like adding a "sata_clk" input to the Red Pitaya platform block "clock sources" options, and carrying the parameterization through the build chain. For starters, you could also open the <build_directory>/myproj/myproj.xpr vivado project and modify it as per the guide you linked, rather than trying to mess with the toolflow straight out the gate. I'm not wildly familiar with the RP platform, so maybe someone else has more wisdom to share. Cheers Jack On Wed, 3 Nov 2021 at 11:34, Haensel, Stefan <[email protected]<mailto:[email protected]>> wrote: > > Hello, > > I try to synchronize several Red Pitayas (RPs) to the same clock. For that RP > has a SATA connector to hand over the clock to the next RP as written here: > https://www.koheron.com/blog/2016/11/29/red-pitaya-cluster<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.koheron.com%2Fblog%2F2016%2F11%2F29%2Fred-pitaya-cluster&data=04%7C01%7Cstefan.haensel%40siemens.com%7C777deb4e80334e267d8c08d99ec991e9%7C38ae3bcd95794fd4addab42e1495d55a%7C1%7C0%7C637715412329206879%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=g19WRaPWtymqwBslZnTYjDs9C0eG%2FvlJcCUu%2Fyw5f3w%3D&reserved=0> > > For that I need to change the PLL of the slave RPs. Is there somewhere a > documentation, which describes how to change IP blocks? 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