On 24 May 2011 22:17, Bruno Cardoso Lopes <[email protected]> wrote: > Add support for ARM ldrexd/strexd intrinsics. ldrexd and strexd both > use register pairs to load/store i64 values. The register pair > constraint specifies that the first register should be even and the > second the following odd. Teach the pre-regalloc LoadStoreOptimizer to > use register allocator hints to respect the constraint and teach the > post-reagalloc to fix the pair (with a very conservative approach) > when the hint fails. A testcase is also present.
Hi Bruno, I'm not proficient enough in the regalloc to analyse that part, but regardless of the intrinsic lowering, I think that's an important change on itself (maybe on a separate patch?). But I was wondering about the need for an intrinsic... First, you declare both ldrexd and strexd but only lowers the former. Are you planning to implement both? And the single/half/word variants, too? Second, I couldn't find ldrex and strex intrinsics, but the instructions are clearly there. If they were there just for disassembly purposes, than we need to be able to lower them somehow. I was wondering if @llvm.atomic.load couldn't trigger LDREX in armv6+ platforms without the need to create new intrinsic... cheers, --renato _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
