On 25 May 2011 04:20, Bruno Cardoso Lopes <[email protected]> wrote: > I see no reason for it go in another separated patch, because it's a > requirement, if it's not in pairs, the instruction is wrong. (...) > I lower both of them, the former using tablegen, the later in iseldag. > I have no plans to add the others, the only reason I'm trying to add > this one is because there's no way to represent the pair restriction > using inline asm.
Ok, just checking. ;) > Because of that, I still think that would be good to have a "ldrexd" > and "strexd" around. But I'm open to any better approach, if there's > one available. Yes, I know. My idea was to use @llvm.atomic.load.i64 (rather than load.add.i64) to map to the same concept. I don't know if other architectures have the atomic load/store instructions, but if they do, it makes sense to be generic. thanks, --renato _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
