Sorry for being late to the thread. 1. Please rename SelectAddrMode7. There is no such addressing mode. We used 1, 2, ..., 6 because that's what earlier ARM doc used, but we really should rename them.
2. Another solution for the register pair issue is to assign them fixed physical registers at isel time. The good thing about it is it eliminate the complexity in ARMLoadStoreOpt. Evan On May 25, 2011, at 4:37 PM, Jakob Stoklund Olesen wrote: > > On May 25, 2011, at 4:26 PM, Bruno Cardoso Lopes wrote: > >> Jakob, I >> agree that regalloc stuff is gross, but since both instructions are >> only used by these intrinsic right now the impact isn't great. Also, >> I'm not sure how to make it cleaner, can you point to some code that >> model the even/odd pair constraint explicitly in a more elegant way? > > Eventually, I would like to do something similar to the QQ register class: > Model the constraint as pseudo-super-registers R0_R1, R2_R3, ... > > So far, this requires pseudo-instructions and tedious register class > definitions. It also affects register allocation compile time by creating > more register aliases. > > Until these problems can be resolved, your solution is fine. > > /jakob > > _______________________________________________ > llvm-commits mailing list > [email protected] > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
