>> H.C. Cron wrote
>> 
>> HCC> As I see the problem, you can not solve it in your way. What you are
>> HCC> doing can be compared with an inverter the output of which is fed 
>> HCC> back to the input. Look at D. D is a constituent of the Reset signal 
>> HCC> and just this Reset signal has to reset D by voltage levels (no edge 
>> HCC> triggering). This will result in the voltage of D to hang somewhere 
>> HCC> between the logic levels. 
>> 
>> are you really sure about that?
>> You have a natural delay in Martin's circuit, since the D output will
>> not instantaneously flip back to the high-state once the reset signal
>> disappears, but only after 8 external clock signals.

HCC> How can you reset D with the D signal itself? These are level 
HCC> signals, no edge trigering. 

as long as the flip-flop of the D-output has not been reset, the
output will stay in its 1-state. When the flip-flop has been reset and
the output - after a certain output delay time (usually some ns), the
output will go back into the 0-state, disabling the reset signal.
The output and thus the reset signal will not - under any
circumstances - take a metastable position in the middle of the supply
voltage, as it does in the case of a feedback inverter, since a low on
the reset does not automatically force the D-output back to the 1-state.
It will stay 0 until a subsequent number of counts have passed the
clock input of the counter.

Since the flip-flops in these counters are essentially identical, a
reset pulse sufficient to reset the flip-flop "D" will also suffice to
reset flip-flops "A" to "C". This is furthermore insured, since the
reset pulse is prolonged by the gate delay of the flip-flop "D" and
will be active until "D" really toggles (the delay tpHL from the
datasheet).

This technique is referred to as "count truncation" in the datasheets
(e.g. Fairchild 74hc393, TI 7490-93

Uwe.

-- 
Author: Uwe Zimmermann
  INET: [EMAIL PROTECTED]

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