Hi Martin,

As I see the problem, you can not solve it in your way. What you are 
doing can be compared with an inverter the output of which is fed 
back to the input. Look at D. D is a constituent of the Reset signal 
and just this Reset signal has to reset D by voltage levels (no edge 
triggering). This will result in the voltage of D to hang somewhere 
between the logic levels. 

The 7493 does not give you much room for playing the game. An option 
would be to use an extra one-shot which is triggered by the condition 
you need. The output of the oneshot will deliver a pulse which can be 
designed long enough to reset the counter. 
A tric, which I don't like, is to charge a capacitor on your 
condition via a diode and use the capacitors voltage as the input of 
a CMOS gate the output of which delivers the reset signal. This way 
of designing however frustrates the design principles of the logic 
family with the consequence that you can not rely on the build in 
noise levels.

Regards, Harry 

>       What I have is a 7493 configured to reset when the count
> reaches 12 or when outputs D and C go high.  At other times, I want
> the 7493 to reset when the count reaches 10 or when outputs D and B go
> high.  For that, I can directly connect D to one reset and the other
> reset could go to a double-pole, single-throw switch with the other
> two terminals of the switch going to B and C.  I wanted the switch,
> however, to be made of digital logic so I only need ground a line to
> change from B--Reset to C--reset.
> -- 
> Author: Martin McCormick
>   INET: [EMAIL PROTECTED]
> 
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-- 
Author: H.C. Croon
  INET: [EMAIL PROTECTED]

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