H.C. Cron wrote HCC> As I see the problem, you can not solve it in your way. What you are HCC> doing can be compared with an inverter the output of which is fed HCC> back to the input. Look at D. D is a constituent of the Reset signal HCC> and just this Reset signal has to reset D by voltage levels (no edge HCC> triggering). This will result in the voltage of D to hang somewhere HCC> between the logic levels.
are you really sure about that? You have a natural delay in Martin's circuit, since the D output will not instantaneously flip back to the high-state once the reset signal disappears, but only after 8 external clock signals. Getting the reset signal from a counter is not very uncommon in the way Martin describes it, I have myself used such circuits and if I'm not completely mistaken it even is part of either the datasheet or the application notes. However, unlike Martin's idea with a switch, I also would prefer a solid logic solution, which would select either the B or C output to contribute to the reset signal. Just doing a quick estimation with normal logic gates you would need at least four gates with different (NOR, NAND) functions. Therefore I would suggest a 2-1 data multiplexer such as 74xx157 (153) 74xx257 (253) These chips offer 4(2) multiplexers which select 1 out of 2(4) input lines to be repeated at the output pin. These are not analog switches and they only work in one direction. Uwe. HCC> The 7493 does not give you much room for playing the game. An option HCC> would be to use an extra one-shot which is triggered by the condition HCC> you need. The output of the oneshot will deliver a pulse which can be HCC> designed long enough to reset the counter. HCC> A tric, which I don't like, is to charge a capacitor on your HCC> condition via a diode and use the capacitors voltage as the input of HCC> a CMOS gate the output of which delivers the reset signal. This way HCC> of designing however frustrates the design principles of the logic HCC> family with the consequence that you can not rely on the build in HCC> noise levels. HCC> Regards, Harry >> What I have is a 7493 configured to reset when the count >> reaches 12 or when outputs D and C go high. At other times, I want >> the 7493 to reset when the count reaches 10 or when outputs D and B go >> high. For that, I can directly connect D to one reset and the other >> reset could go to a double-pole, single-throw switch with the other >> two terminals of the switch going to B and C. I wanted the switch, >> however, to be made of digital logic so I only need ground a line to >> change from B--Reset to C--reset. >> -- >> Author: Martin McCormick >> INET: [EMAIL PROTECTED] >> >> Fat City Network Services -- 858-538-5051 http://www.fatcity.com >> San Diego, California -- Mailing list and web hosting services >> --------------------------------------------------------------------- >> To REMOVE yourself from this mailing list, send an E-Mail message >> to: [EMAIL PROTECTED] (note EXACT spelling of 'ListGuru') and in >> the message BODY, include a line containing: UNSUB CHIPDIR-L >> (or the name of mailing list you want to be removed from). You may >> also send the HELP command for other information (like subscribing). >> -- Author: Uwe Zimmermann INET: [EMAIL PROTECTED] Fat City Network Services -- 858-538-5051 http://www.fatcity.com San Diego, California -- Mailing list and web hosting services --------------------------------------------------------------------- To REMOVE yourself from this mailing list, send an E-Mail message to: [EMAIL PROTECTED] (note EXACT spelling of 'ListGuru') and in the message BODY, include a line containing: UNSUB CHIPDIR-L (or the name of mailing list you want to be removed from). You may also send the HELP command for other information (like subscribing).
