> here is a weered problem i stuck with developing a board of mine. > it's a very heavy loaded board with many FPGA's on that "eat" a lot of > power (100W) > the problem is that those FPGA's do a heavy work once every 2msec wich > creates power drop of about 0.2 volt. > it results with the voltage looking like this: > /\ ___/\ ___ > \/ \/ > where the mean voltage is 3.3V
Hi Michael, is the horizontal line the 3.3V? In that case I do not only see a power drop, but also a power voltage rise? That means that something may be reflecting, too much inductance etc. Is it a multilayer with two power planes? You must use several capacitors, spread all over the board. But do NOT place them neatly as you used to learn at school. All those neat distances of th same length lead to a lot of circuits with the same resonance frequency. If this is what you have, user smaller and/or larger capaitors on several places. Regards, Pieter Hoeben > anyone know how to deal with thease voltage dropout (thy cause > malfunctioning of the curcit) > Author: Michael Gefen > INET: [EMAIL PROTECTED] ______________________________________________ Hoeben Electronics Phone: +31 6 51590081 Ronkert 44 Fax: +31 13 5096025 5094 EW Lage Mierde Private: +31 13 5096200 The Netherlands E-mail: [EMAIL PROTECTED] http://www.hoeben.com ______________________________________________ -- Author: Pieter Hoeben INET: [EMAIL PROTECTED] Fat City Hosting, San Diego, California -- http://www.fatcity.com --------------------------------------------------------------------- To REMOVE yourself from this mailing list, send an E-Mail message to: [EMAIL PROTECTED] (note EXACT spelling of 'ListGuru') and in the message BODY, include a line containing: UNSUB CHIPDIR-L (or the name of mailing list you want to be removed from). You may also send the HELP command for other information (like subscribing).
