> Hi,
> the board is 18 layer board.
> all the powering is done using the folowing scheme:
> 1. all major power consumers have a sepparate "iland" under it (in one
> of the layers) connected to the main supply (ie 3.3 / 1.5V) with a
> Ferrite Bead, and a large capasitor (typicly 47uF tantalum) on both
> sides of te bead. in addition there are decoupling capacitors (0.1uf/
> 22pf) on each power terminal of the FPGA.
> All of the parts run from 120MHz clock distributed from CY2309.
> replacing the clock splitter with an industrial device, reduced the
> amounty of errors i get from the FPGAs.
> the power consuption is as folowing: showing the power line and
> consumption (where H stand for High and L for Low)
> /\  __/\  __
>   \/    \/
> LHHHHHLHHHHH
> 
> the rise of the graph is on LOW power consuption (i think it got some
> thing to do with the responce time of the Power Supply i.e.: it feels
> high current, but take time to stabilize the voltage level, so we see
> power drop. then the current fall and we see a power rise)

To get an idea of the frequency, what is the risetime, up/down time
and falltime of this puls?

Pieter





>  
> 
> Pieter Hoeben wrote:
> 
> >>here is a weered problem i stuck with developing a board of mine.
> >>it's a very heavy loaded board with many FPGA's on that "eat" a lot of
> >>power (100W)
> >>the problem is that those FPGA's do a heavy work once every 2msec wich
> >>creates power drop of about 0.2 volt.
> >>it results with the voltage looking like this:
> >>/\   ___/\   ___
> >>   \/         \/
> >>where the mean voltage is 3.3V
> >>
> >
> >Hi Michael, is the horizontal line the 3.3V? In that case
> >I do not only see a power drop, but also a power voltage rise?
> >That means that something may be reflecting, too much
> >inductance etc. Is it a multilayer with two power planes?
> >
> >You must use several capacitors, spread all over the board.
> >But do NOT place them neatly as you used to learn at school.
> >All those neat distances of th same length lead to a lot of
> >circuits with the same resonance frequency. If this is what
> >you have, user smaller and/or larger capaitors on several places.
> >
> >Regards,
> >
> >Pieter Hoeben
> >
> >
> >>anyone know how to deal with thease voltage dropout (thy cause
> >>malfunctioning of the curcit)
> >>Author: Michael Gefen
> >>  INET: [EMAIL PROTECTED]
> >>
> >______________________________________________
> >
> >  Hoeben Electronics          Phone:   +31 6 51590081
> >  Ronkert 44                  Fax:     +31 13 5096025
> >  5094 EW Lage Mierde         Private: +31 13 5096200
> >  The Netherlands             E-mail:  [EMAIL PROTECTED]
> >  http://www.hoeben.com      
> >______________________________________________
> >
> >
> >
> 
> -- 
> Author: Michael Gefen
>   INET: [EMAIL PROTECTED]
> 
> Fat City Hosting, San Diego, California -- http://www.fatcity.com
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> 


______________________________________________

  Hoeben Electronics     Phone:   +31 6 51590081
  Ronkert 44             Fax:     +31 13 5096025
  5094 EW Lage Mierde    Private: +31 13 5096200
  The Netherlands        E-mail:  [EMAIL PROTECTED]
  http://www.hoeben.com 
______________________________________________


-- 
Author: Pieter Hoeben
  INET: [EMAIL PROTECTED]

Fat City Hosting, San Diego, California -- http://www.fatcity.com
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