18 layers - wow... But I am quite certain that the capacitors you have at the supply leads of the FPGAs are insufficient!
In the case of a sudden power jump, the supply lines have to support the additional current demanded by the chip. Since all traces on a PCB (and especially if you have additional ferrite beads around!) act as inductors, they try to keep the current CONSTANT! The role of the decoupling capacitors at the leads of the chips is not to short-circuit HF interference - as one might expect, but to supply the chip with enough current until the traces themselves adapt to the new current. If the capacitor is too small, two things will happen: a) the voltage over the supply leads of the chip will drop b) once the traces provide more current and the chip again lowers its demand, the supply voltage at the leads will rise to possibly dangerous levels Does this sound familiar??? Forget about the tantalums. They are not good to deliver any short-term power anyway. But they are nice to smoothen out supply voltage variations and 50/60Hz noise... In order to get a hum on the appropiate size of the capacitors, let's do a simple calculation (from Digital Systems Engineering, ISBN 0-521-59292-5, Cambridge University Press, p249 ff): A chip with 20 modules of each 50000 gate equivalents draws an average of 12A at 3.3V with sudden peaks of 30A and time constants in the order of 10ns. The power planes on the board are assumed to have 80pH of inductance and 240A average current. These 80pH are indeed neglible to the leads of the capacitors, the internal inductance of the capacitors and the leads of the chip. A 100nF chip capacitor has about 1nH in inductance! The final design in this case ended up with one 100nF ceramic chip at each supply pin (20 per FPGA) a maximum of 2nH total inductance between the ceramic chips and the electrolytics a total of 5 low-ESR (not tantalum!!!) electrolytics close to each FPGA, 22uF each a maximum of 200nH inductance between the chip and the on-board step-down regulator I am not even sure if your 22pF capacitors don't make it worse - is this from the datasheet of the FPGAs or a try of yours to reduce the spikes? Uwe. > Hi, > the board is 18 layer board. > all the powering is done using the folowing scheme: > 1. all major power consumers have a sepparate "iland" under it (in one > of the layers) connected to the main supply (ie 3.3 / 1.5V) with a > Ferrite Bead, and a large capasitor (typicly 47uF tantalum) on both > sides of te bead. in addition there are decoupling capacitors (0.1uf/ > 22pf) on each power terminal of the FPGA. > All of the parts run from 120MHz clock distributed from CY2309. > replacing the clock splitter with an industrial device, reduced the > amounty of errors i get from the FPGAs. > the power consuption is as folowing: showing the power line and > consumption (where H stand for High and L for Low) > /\ __/\ __ > \/ \/ > LHHHHHLHHHHH > the rise of the graph is on LOW power consuption (i think it got some > thing to do with the responce time of the Power Supply i.e.: it feels > high current, but take time to stabilize the voltage level, so we see > power drop. then the current fall and we see a power rise) > Pieter Hoeben wrote: >>>here is a weered problem i stuck with developing a board of mine. >>>it's a very heavy loaded board with many FPGA's on that "eat" a lot of >>>power (100W) >>>the problem is that those FPGA's do a heavy work once every 2msec wich >>>creates power drop of about 0.2 volt. >>>it results with the voltage looking like this: >>>/\ ___/\ ___ >>> \/ \/ >>>where the mean voltage is 3.3V >>> >> >>Hi Michael, is the horizontal line the 3.3V? In that case >>I do not only see a power drop, but also a power voltage rise? >>That means that something may be reflecting, too much >>inductance etc. Is it a multilayer with two power planes? >> >>You must use several capacitors, spread all over the board. >>But do NOT place them neatly as you used to learn at school. >>All those neat distances of th same length lead to a lot of >>circuits with the same resonance frequency. If this is what >>you have, user smaller and/or larger capaitors on several places. >> >>Regards, >> >>Pieter Hoeben >> >> >>>anyone know how to deal with thease voltage dropout (thy cause >>>malfunctioning of the curcit) >>>Author: Michael Gefen >>> INET: [EMAIL PROTECTED] >>> >>______________________________________________ >> >> Hoeben Electronics Phone: +31 6 51590081 >> Ronkert 44 Fax: +31 13 5096025 >> 5094 EW Lage Mierde Private: +31 13 5096200 >> The Netherlands E-mail: [EMAIL PROTECTED] >> http://www.hoeben.com >>______________________________________________ >> >> >> -- Author: Uwe Zimmermann INET: [EMAIL PROTECTED] Fat City Hosting, San Diego, California -- http://www.fatcity.com --------------------------------------------------------------------- To REMOVE yourself from this mailing list, send an E-Mail message to: [EMAIL PROTECTED] (note EXACT spelling of 'ListGuru') and in the message BODY, include a line containing: UNSUB CHIPDIR-L (or the name of mailing list you want to be removed from). You may also send the HELP command for other information (like subscribing).
