(I tried sending this yesterday but, because of a slight difference in my 
return email address, it seems to have been quietly dropped by the server)


The advice regarding the ceramic bypass capacitors is good as far as it
goes, but, if your problem is a power supply which compensates slowly
for load changes, you might try some bulk capacitance across the 3.3V
input to the board as well (a large electrolytic). This should partly
take up the initial changes in current so that the power supply has the
time to respond and prevent serious falls and rises in the output
voltage.
If it is slow response in the supply, you should see the voltage spikes
at its output not just near the FPGA.
If adding bulk capacitance does not work, you may have to consider using a 
better power supply to provide the 3.3V



On Sat, 2005-09-17 at 15:39 -0800, Uwe Zimmermann wrote:
> ...plenty of fast capacitors (ceramic, not electrolytic) close to the
> supply pins of the chips, short and wide power lines...
> 
>    Uwe.
> 
> 
> > hi,
> > here is a weered problem i stuck with developing a board of mine.
> > it's a very heavy loaded board with many FPGA's on that "eat" a lot of
> > power (100W)
> > the problem is that those FPGA's do a heavy work once every 2msec wich
> > creates power drop of about 0.2 volt.
> > it results with the voltage looking like this:
> > /\   ___/\   ___
> >    \/         \/
> 
> > where the mean voltage is 3.3V
> 
> > anyone know how to deal with thease voltage dropout (thy cause
> > malfunctioning of the curcit)
> 
> > regars, Michael
> 
> 
-- 
Bob Mitchell
PO Box 68                               Phone   (+61 2) 9449 4736
(21 Hudson Close)                       Fax     (+61 2) 9449 1976
Turramurra, 2074                        Mobile      0411554117
NSW, Australia                          Email   [EMAIL PROTECTED]


-- 
Author: Robert Mitchell
  INET: [EMAIL PROTECTED]

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