anchao commented on code in PR #12178:
URL: https://github.com/apache/nuttx/pull/12178#discussion_r1580586106
##########
arch/risc-v/src/common/riscv_internal.h:
##########
@@ -294,11 +297,25 @@ int riscv_check_pmp_access(uintptr_t attr, uintptr_t
base, uintptr_t size);
int riscv_configured_pmp_regions(void);
int riscv_next_free_pmp_region(void);
+/* RISC-V Memorymap Config **************************************************/
+
+static inline void riscv_set_basestack(uintptr_t base, uintptr_t size)
+{
+ unsigned int i = 0;
Review Comment:
```suggestion
unsigned int i;
```
##########
arch/risc-v/src/common/riscv_macros.S:
##########
@@ -364,3 +364,35 @@
csrr \out, CSR_MHARTID
#endif
.endm
+
+/****************************************************************************
+ * Name: riscv_set_inital_sp
+ *
+ * Description:
+ * Set inital sp for riscv core. This function should be only called
+ * when initing.
+ *
+ * sp (stack top) = sp base + idle stack size * hart id
+ * sp (stack base) = sp (stack top) + idle stack size * - XCPTCONTEXT_SIZE
+ *
+ * Note: The XCPTCONTEXT_SIZE byte after stack base is reserved for
+ * up_initial_state since we are already running and using
+ * the per CPU idle stack.
+ * Parameter:
+ * base - Pointer to where the stack is allocated (e.g. _ebss)
+ * size - Stack size for pre cpu to allocate
+ * size - Hart id register of this hart (Usually a0)
+ *
+ ****************************************************************************/
+.macro riscv_set_inital_sp base, size, hartid
+ la t0, \base
+ li t1, \size
+ mul t1, \hartid, t1
+ add t0, t0, t1
+
+ /* ensure the last XCPTCONTEXT_SIZE is reserved */
+
+ li t1, STACK_ALIGN_DOWN(\size - XCPTCONTEXT_SIZE)
Review Comment:
CPU0 could use stack top without XCPTCONTEXT_SIZE
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