anchao commented on code in PR #12178:
URL: https://github.com/apache/nuttx/pull/12178#discussion_r1580730984


##########
arch/risc-v/src/common/riscv_macros.S:
##########
@@ -364,3 +364,35 @@
   csrr    \out, CSR_MHARTID
 #endif
 .endm
+
+/****************************************************************************
+ * Name: riscv_set_inital_sp
+ *
+ * Description:
+ *   Set inital sp for riscv core. This function should be only called
+ *   when initing.
+ *
+ *   sp (stack top) = sp base + idle stack size * hart id
+ *   sp (stack base) = sp (stack top) + idle stack size * - XCPTCONTEXT_SIZE
+ *
+ *   Note: The XCPTCONTEXT_SIZE byte after stack base is reserved for
+ *         up_initial_state since we are already running and using
+ *         the per CPU idle stack.
+ * Parameter:
+ *   base - Pointer to where the stack is allocated (e.g. _ebss)
+ *   size - Stack size for pre cpu to allocate
+ *   size - Hart id register of this hart (Usually a0)
+ *
+ ****************************************************************************/
+.macro riscv_set_inital_sp base, size, hartid
+  la      t0, \base
+  li      t1, \size
+  mul     t1, \hartid, t1
+  add     t0, t0, t1
+
+  /* ensure the last XCPTCONTEXT_SIZE is reserved */
+
+  li   t1, STACK_ALIGN_DOWN(\size - XCPTCONTEXT_SIZE)

Review Comment:
   > This is prepared for boot with cores other than 0.
   
   So, where is the idle stack for CPU0? I just reviewed your changes roughly 
and all XXX_RV_IDLESTACK_TOP should have been removed.
   
   > In addition, I have seen 
[`xcp->regs`](https://github.com/apache/nuttx/blob/master/arch/risc-v/src/common/riscv_initialstate.c#L135)
 always point to the XCPTCONTEXT_SIZE offset of the topstack. I have no idea 
about this truth you have pointed out, although I know it works. Do I miss 
something?
   
   CPU0 does not need to reserve XCPTCONTEXT_SIZE since the first idle 
task(CPU0) is running task, which does not to need to restore the context. the 
area of XCPTCONTEXT is mainly to allow the task to restore the correct 
parameters of initialization registers if context switch.
   



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