xiaoxiang781216 commented on code in PR #12178:
URL: https://github.com/apache/nuttx/pull/12178#discussion_r1581992336
##########
arch/risc-v/src/common/riscv_internal.h:
##########
@@ -294,6 +294,18 @@ int riscv_check_pmp_access(uintptr_t attr, uintptr_t base,
uintptr_t size);
int riscv_configured_pmp_regions(void);
int riscv_next_free_pmp_region(void);
+/* RISC-V Memorymap Config **************************************************/
+
+static inline void riscv_set_basestack(uintptr_t base, uintptr_t size)
+{
+ unsigned int i;
+
+ for (i = 0; i < CONFIG_SMP_NCPUS; i++)
+ {
+ g_cpux_idlestack[i] = (const uint8_t *)(base + size * i);
Review Comment:
why not initialize the array at the definition place?
##########
arch/risc-v/src/common/riscv_ipi.h:
##########
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/risc-v/src/common/riscv_ipi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H
+#define __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "riscv_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+static inline void riscv_ipi_send(int cpu)
+{
+#if defined(RISCV_IPI)
Review Comment:
remove, it's better to generate the.compiler error instead runtime panic.
##########
arch/risc-v/src/common/riscv_macros.S:
##########
@@ -364,3 +364,45 @@
csrr \out, CSR_MHARTID
#endif
.endm
+
+/****************************************************************************
+ * Name: riscv_set_inital_sp
+ *
+ * Description:
+ * Set inital sp for riscv core. This function should be only called
+ * when initing.
+ *
+ * sp (stack top) = sp base + idle stack size * hart id
+ * sp (stack base) = sp (stack top) + idle stack size * - XCPTCONTEXT_SIZE
+ *
+ * Note: The XCPTCONTEXT_SIZE byte after stack base is reserved for
+ * up_initial_state since we are already running and using
+ * the per CPU idle stack.
+ *
+ * TODO: Support non-zero boot hart.
+ *
+ * Parameter:
+ * base - Pointer to where the stack is allocated (e.g. _ebss)
+ * size - Stack size for pre cpu to allocate
+ * size - Hart id register of this hart (Usually a0)
Review Comment:
size to hartid
##########
arch/risc-v/src/common/riscv_ipi.h:
##########
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/risc-v/src/common/riscv_ipi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H
+#define __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "riscv_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+static inline void riscv_ipi_send(int cpu)
+{
+#if defined(RISCV_IPI)
+ putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu));
+#else
+ PANIC();
+#endif
+}
+
+static inline void riscv_ipi_clear(int cpu)
+{
+#if defined(RISCV_IPI)
Review Comment:
ditto
##########
arch/risc-v/src/common/riscv_macros.S:
##########
@@ -364,3 +364,45 @@
csrr \out, CSR_MHARTID
#endif
.endm
+
+/****************************************************************************
+ * Name: riscv_set_inital_sp
+ *
+ * Description:
+ * Set inital sp for riscv core. This function should be only called
+ * when initing.
+ *
+ * sp (stack top) = sp base + idle stack size * hart id
+ * sp (stack base) = sp (stack top) + idle stack size * - XCPTCONTEXT_SIZE
+ *
+ * Note: The XCPTCONTEXT_SIZE byte after stack base is reserved for
+ * up_initial_state since we are already running and using
+ * the per CPU idle stack.
+ *
+ * TODO: Support non-zero boot hart.
+ *
+ * Parameter:
+ * base - Pointer to where the stack is allocated (e.g. _ebss)
+ * size - Stack size for pre cpu to allocate
+ * size - Hart id register of this hart (Usually a0)
+ *
+ ****************************************************************************/
+.macro riscv_set_inital_sp base, size, hartid
+ la t0, \base
+ li t1, \size
+ mul t1, \hartid, t1
+ add t0, t0, t1
+
+ /* ensure the last XCPTCONTEXT_SIZE is reserved for non boot CPU */
+
+ bnez \hartid, 998f
Review Comment:
why not remove the reserve from up_initial_state to make the code mofe
consistent? or skip calling riscv_set_inital_sp for boot cpu.
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