raiden00pl commented on code in PR #16904:
URL: https://github.com/apache/nuttx/pull/16904#discussion_r2300538050


##########
arch/arm/src/stm32h5/stm32_adc.h:
##########
@@ -463,10 +463,88 @@
 #  endif
 #endif
 
+/* IOCTL Support */
+
+#define ANIOC_STM32H5_WDOG_CFG       _ANIOC(AN_STM32H5_FIRST + 0)
+#define ANIOC_STM32H5_WDOG2_CFG      _ANIOC(AN_STM32H5_FIRST + 1)
+#define ANIOC_STM32H5_WDOG3_CFG      _ANIOC(AN_STM32H5_FIRST + 2)
+#define ANIOC_STM32H5_WDOG_GET_EVENT _ANIOC(AN_STM32H5_FIRST + 3) /* OUT: 
struct stm32_adc_wdg_event_s* */
+#define ANIOC_STM32H5_WDOG_SIGCFG    _ANIOC(AN_STM32H5_FIRST + 4) /*  IN: 
struct stm32_adc_sigcfg_s*  */
+
+/* Watchdog Event Queue Support */
+
+#define WQ_LEN    128
+#define WQ_MASK   (WQ_LEN - 1)
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
 
+/* STM32H5 ADC channel configuration */
+
+struct stm32_adc_channel_s
+{
+  uint8_t chan;                 /* Channel Number */
+  uint32_t p_gpio;              /* P GPIO */
+  uint32_t n_gpio;              /* N GPIO */
+  uint8_t tsamp:3;              /* Sampling time */
+  uint8_t mode:1;               /* Single-ended 0 or differential mode 1 */
+  uint8_t injected:1;           /* Regular 0 or Injected 1 */
+  uint8_t _res:3;               /* Reserved */
+};

Review Comment:
   This is not compatible with other STM32 families. I don't know if this is 
the right approach. Also GPIO is configured on board level, so there is no 
reason to pass this to lower-half driver.



##########
arch/arm/src/stm32h5/stm32_adc.c:
##########
@@ -624,6 +773,195 @@ static void adc_wdog_enable(struct stm32_dev_s *priv)
   adc_putreg(priv, STM32_ADC_IER_OFFSET, regval);
 }
 
+/****************************************************************************
+ * Name: adc_wdog1_configure
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+static int adc_wdog1_configure(struct stm32_dev_s *priv,
+                                struct stm32_adc_watchdog1_cfg_s *cfg)

Review Comment:
   This should be generalized and be a single function for all ADC instances. 
There's no point in duplicating the logic.



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