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commit 93db0083dfcaa51b6f1b12f252e0feb9d976d991 Author: raiden00pl <[email protected]> AuthorDate: Mon Sep 14 12:55:29 2026 +0200 arch/arm/stm32c0: Add USB device support add USB device support for STM32C0 Assisted-by: Claude Code Signed-off-by: raiden00pl <[email protected]> --- Documentation/guides/stm32_ports.rst | 8 ++++---- Documentation/platforms/arm/stm32c0/index.rst | 4 ++-- arch/arm/src/stm32c0/Kconfig | 5 ++++- arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h | 5 +++++ arch/arm/src/stm32c0/hardware/stm32c0_rcc.h | 7 ++++--- arch/arm/src/stm32c0/stm32_rcc.c | 6 ++++++ arch/arm/src/stm32c0/stm32c0_rcc.c | 21 +++++++++++++++++++++ 7 files changed, 46 insertions(+), 10 deletions(-) diff --git a/Documentation/guides/stm32_ports.rst b/Documentation/guides/stm32_ports.rst index 2f71ac004df..68aa193af53 100644 --- a/Documentation/guides/stm32_ports.rst +++ b/Documentation/guides/stm32_ports.rst @@ -228,7 +228,7 @@ SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c SYSCFG to be done not supported TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m0_v4.c -USB device not supported +USB device v2 arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c ============ ============ ================================================= @@ -296,7 +296,7 @@ SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c SYSCFG to be done not supported TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m0_v3.c -USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c +USB device v1 arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c ============ ============ ================================================= @@ -554,7 +554,7 @@ SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c SYSCFG to be done not supported TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m0_v4.c -USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c +USB device v2 arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c ============ ============ ================================================= @@ -657,7 +657,7 @@ RTC RTCC M0 not supported SPI/I2S v1 arch/arm/src/common/stm32/stm32_spi_m0_v1.c TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m0_v3.c -USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c +USB device v1 arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c ============ ============ ================================================= diff --git a/Documentation/platforms/arm/stm32c0/index.rst b/Documentation/platforms/arm/stm32c0/index.rst index f989b889c47..4a05bf0b827 100644 --- a/Documentation/platforms/arm/stm32c0/index.rst +++ b/Documentation/platforms/arm/stm32c0/index.rst @@ -9,7 +9,7 @@ Supported MCUs MCU Support Note ========= ======= ======================= STM32C051 Yes -STM32C071 Yes USB not supported yet +STM32C071 Yes STM32C091 Yes STM32C092 Yes FDCAN not supported yet ========= ======= ======================= @@ -41,7 +41,7 @@ I2C Yes USART Yes SPI Yes FDCAN Yes -USB No +USB Yes Device only (STM32C071) ========== ======= ===== Supported Boards diff --git a/arch/arm/src/stm32c0/Kconfig b/arch/arm/src/stm32c0/Kconfig index 6d3363b20d0..be28290098d 100644 --- a/arch/arm/src/stm32c0/Kconfig +++ b/arch/arm/src/stm32c0/Kconfig @@ -252,7 +252,8 @@ config STM32_STM32C0 select STM32_HAVE_IP_TIMERS_M0_V1 select STM32_HAVE_IP_USART_V4 select STM32_HAVE_IP_WDG_M0_V1 - select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBDEV_M0_V2 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 @@ -269,6 +270,8 @@ config ARCH_CHIP_STM32C071XX bool select STM32_STM32C0 select STM32_HAVE_USBDEV + select STM32_HAVE_HSI48 + select STM32_HAVE_CRS config ARCH_CHIP_STM32C091XX bool diff --git a/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h index 5d8805236ed..6ee2e2c32be 100644 --- a/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h @@ -351,4 +351,9 @@ #define GPIO_TIM17_CH1NOUT_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4) #define GPIO_TIM17_CH1NOUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7) +/* USB */ + +#define GPIO_USB_DM (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11) +#define GPIO_USB_DP (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN12) + #endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H */ diff --git a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h index 2ead7025a00..aa8765f001c 100644 --- a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h @@ -347,9 +347,10 @@ /* RCC peripherals independent clock configuration register 2 */ -#define RCC_CCIPR2_USBSEL_SHIFT (12) /* Bit 12: SB clock source selection */ -#define RCC_CCIPR2_USBSEL_HSIUSB48 (0 << RCC_CCIPR2_USBSEL_SHIFT) -#define RCC_CCIPR2_USBSEL_HSE (1 << RCC_CCIPR2_USBSEL_SHIFT) +#define RCC_CCIPR2_USBSEL_SHIFT (12) /* Bit 12: USB clock source selection */ +#define RCC_CCIPR2_USBSEL_MASK (1 << RCC_CCIPR2_USBSEL_SHIFT) +# define RCC_CCIPR2_USBSEL_HSIUSB48 (0 << RCC_CCIPR2_USBSEL_SHIFT) +# define RCC_CCIPR2_USBSEL_HSE (1 << RCC_CCIPR2_USBSEL_SHIFT) /* Clock configuration register 1 */ diff --git a/arch/arm/src/stm32c0/stm32_rcc.c b/arch/arm/src/stm32c0/stm32_rcc.c index 4c847902807..c5e313789ff 100644 --- a/arch/arm/src/stm32c0/stm32_rcc.c +++ b/arch/arm/src/stm32c0/stm32_rcc.c @@ -54,6 +54,12 @@ # endif #endif +/* HSIUSB48 is the only 48MHz USB clock source on STM32C0 */ + +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# define STM32_USE_HSI48 +#endif + static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, "Configure BOARD_LOOPSPERMSEC to non-default value."); diff --git a/arch/arm/src/stm32c0/stm32c0_rcc.c b/arch/arm/src/stm32c0/stm32c0_rcc.c index c46c41befdf..5ef674dc583 100644 --- a/arch/arm/src/stm32c0/stm32c0_rcc.c +++ b/arch/arm/src/stm32c0/stm32c0_rcc.c @@ -195,6 +195,12 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_USBEN; #endif +#if defined(CONFIG_STM32_CRS) || defined(STM32_USE_HSI48) + /* Clock recovery system clock enable */ + + regval |= RCC_APB1ENR_CRSEN; +#endif + #ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ @@ -458,6 +464,15 @@ static void stm32_stdclockconfig(void) regval |= STM32_FDCAN1_SEL; putreg32(regval, STM32_RCC_CCIPR1); #endif + +#ifdef CONFIG_STM32_USB + /* USB kernel clock from HSIUSB48 */ + + regval = getreg32(STM32_RCC_CCIPR2); + regval &= ~RCC_CCIPR2_USBSEL_MASK; + regval |= RCC_CCIPR2_USBSEL_HSIUSB48; + putreg32(regval, STM32_RCC_CCIPR2); +#endif } #endif @@ -471,6 +486,12 @@ static inline void rcc_enableperipherals(void) rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); + +#ifdef STM32_USE_HSI48 + /* Enable HSIUSB48 clocking for USB */ + + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); +#endif } /****************************************************************************
